关于铜网印刷红胶在SMT中的应用

在红胶工艺制程中,很多工厂都选用了点胶机点胶或者O．2—0．3mm的钢网印刷红胶．但对于需要先自插元件后再贴片且贴片点数较多的产品来讲．点胶机点胶效率太低而钢网印刷是无法完成的。当然有些工厂选择先贴片再自插元件,这样在自插元件时对贴片元件又存对应力损坏及掉件的危险。     

陶瓷表面状态对底部填充胶流动性影响研究

由于陶瓷外壳表面会做氧化铝涂层,这种处理会对底部填充胶的扩散性能造成影响。研究了底部填充胶在不同表面状态的陶瓷外壳上的扩散状态。这对底部填充工艺的发展具有重要的意义。     

助焊剂残留对底部填充粘接强度的影响

随着封装工艺的不断发展,芯片I/O数越来越多,高密度芯片封装必须采用倒装焊的形式。底部填充作为芯片倒装焊封装后的加固工艺,填充胶与倒装焊使用的助焊剂的兼容性对于研究倒装焊电路的长期可靠性至关重要。分析了底部填充胶与助焊剂的兼容性,以及助焊剂的残留对底部填充胶加固效果的影响。若助焊剂清洗不干净,会导致底部填充胶的粘接力下降,影响器件的质量。     

全自动金丝球焊机的改造及应用

随着IC封装材料和技术的进步,产品引脚、焊线、焊盘尺寸正逐渐变小,芯片上焊盘间距不断减小,早期的全自动金丝球焊机已不能满足现有产品的工艺和质量要求,特提出将其改造为点胶机的设想。简要介绍了全自动金丝球焊机改造成时间/压力型全自动点胶机的系统组成和工作原理,以及其在IC封装芯片表面点胶特殊工艺中的应用,并对优缺点、影响点胶质量的因素等进行了分析,提出了改进提高的措施。     

FPA探测器微细间隙填充工艺研究

介绍了倒焊器件填充工艺原理,分析了胶水粘度、放置时间、填充温度和填充速度对填充效果的影响.在常温条件下,选用的胶水放置时间不超过1h,填充速度为0.20 mg/min时,FPA(焦平面阵列)探测器有效区域的填充率达到100％,测试合格率大于95％.     

底部填充工艺探讨

底部填充工艺是倒装芯片封装过程中的一个必不可少而且很关键的组成部分,底部填充工艺的成败将直接影响到封装的可靠性。本文针对底部填充工艺中需考虑的多个方面,如分配模式、胶水体积计算、硬件选择等,阐述如何改进工艺,增强底部填充的自动生产的能力。     

为CSP和BGA设计的底部填充剂的工艺优势

底部填充剂技术推广到表面安装元件工艺上，如CSP和BGA。为CSP/BGA设计的底部填充剂具有操作和产量方面的优越性，易于储存，使用寿命长，可在线快速固化，同时也降低了粘度和比重，提高了点胶速度和流动速度；当然，也牺牲了一些材料的特性，产生较高的CTE。     

倒装芯片放置工艺的设计分析

对倒装芯片不流动底部填充胶进行压迫流动填充,底部填料会对倒装芯片产生流体静态压力,阻碍芯片向下放置。根据牛顿流体挤压流动的静态近似分析估算出底部填料对芯片的作用力,分别计算在两种不同工艺条件下放置压力达到最大时,两种不同规格芯片与基板的间隔距离,比较与芯片凸点高度,然后计算使芯片凸点与基板键合区实现接触所需放置压力的最小保持时间,从正反两个方面讨论关键参数等对倒装芯片工艺设计影响。     

使用回流填充胶的FC组装

引言 传统的共晶焊料filp chip组装,在芯片贴放前有两种施加助焊剂的方法:一种是施加在基板上,另一种是将芯片焊凸浸在一层助焊剂薄膜中。后一种方法提供更好的“连接力”(“Tack”),因此回流前芯片偏移的可能较小,另一方面,贴片前施加助焊剂可能有助于提高产能。这两种方法在回流焊接时都需要有氮气的环境。 如图1,回流后,必须用适合的填充胶对硅片进行底部填充,在毛细作用下填充胶会流进芯片底部。免清洗助焊剂的残留物既影响底部填充时的润湿及流动,又     

电子组装喷射点胶过程流体特性CFD模拟分析

喷射点胶技术是电子组装的核心技术,针对如何喷射小直径胶点以满足微电子封装要求这一问题。文中基于气压驱动点胶阀的工作原理,建立顶针和喷嘴碰撞结构二维几何模型,采用CFD计算机流体动力学分析软件对点胶过程中喷嘴口胶水喷射速度、密闭内腔胶水液压进行仿真模拟分析。数值仿真结果表明,顶针几何外形、顶针运动行程及喷嘴张角是影响胶水喷射速度的主要因素,喷射胶点的直径大小是由这些影响因素决定的。     

Comparing the Impacts of the Capillary and the Molded Underfill Process on the Reliability of the Flip-Chip BGA

In the assembly process for the conventional capillary underfill (CUF) flip-chip ball grid array (FCBGA) packaging the underfill dispensing creates bottleneck. The material property of the underfill, the dispensing pattern and the curing profile all have a significant impact on the flip-chip packaging reliability. Due to the demand for high performance in the CPU, graphics and communication market, the large die size with more integrated functions using the low-K chip must meet the reliability criteria and the high thermal dissipation. In addition, the coplanarity of the flip-chip package has become a major challenge for large die packaging. This work investigates the impact of the CUF and the novel molded underfill (MUF) processes on solder bumps, low-K chip and solder ball stress, packaging coplanarity and reliability. Compared to the conventional CUF FCBGA, the proposed MUF FCBGA packaging provides superior solder bump protection, packaging coplanarity and reliability. This strong solder bump protection and high packaging reliability is due to the low coefficient of thermal expansion and high modulus of the molding compound. According to the simulation results, the maximum stress of the solder bumps, chip and packaging coplanarity of the MUF FCBGA shows a remarkable improvement over the CUF FCBGA, by 58.3%, 8.4%, and 41.8% (66 $mu {rm m}$), respectively. The results of the present study indicates that the MUF packaging is adequate for large die sizes and large packaging sizes, especially for the low-K chip and all kinds of solder bump compositions such as eutectic tin-lead, high lead, and lead free bumps.      

Underfill of flip chip on organic substrate: viscosity, surface tension, and contact angle

In flip-chip packaging, an underfill is dispensed on one or two adjacent sides of the die. The underfill is driven by a capillary flow to fill the gap between the die and substrate. The application of an underfill reduces the stress to solder bumps and enhances the reliability of the solder joints. Underfill materials consist of epoxy or cyanate ester resins, catalyst, crosslinker, wetting agent, pigment, and fillers. Underfill materials are highly filled with the filler loading ranging from 40% to 70%. In terms of underfill material processing, fast flow and curing are desired for high throughput. The viscosity, surface tension, and contact angle are key material properties affecting the gap filling process. In order to achieve fast filling, it is required that an underfill material has low viscosity and low contact angle at dispensing temperatures. Due to curing of an underfill material at dispensing temperature, the viscosity increases with time, which complicates the underfill flow process. The rheological behavior of several underfill materials was experimentally studied. All the underfill materials showed strong temperature dependence in viscosity before the curing. The time dependent viscosity and curing of underfill materials were examined by a dynamic time sweep test. The effects of viscosity and curing behavior of underfill materials on underfill material processing were investigated. The material with a longer gel time had more stable viscosity at room temperature, and therefore longer pot life. Experimental methods were developed to measure the surface tension and the contact angle of underfills at temperatures over 100 °C. Results showed that the contact angle for underfill on a substrate was time dependent. The interaction between underfill and substrate affects not only gap filling, but also filleting. The effect of surface energies of flip-chip substrates on wetting angles was also studied. Experiment results showed that for the same underfill, the higher the surface energy of substrate, the better the filleting.     

Package design and materials selection optimization for overmolded flip chip packaging

In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages.     

Wafer-applied underfill: flip-chip assembly and reliability

Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller, lighter, and less expensive packages, and flip-chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense and cure step is not a typical process for a surface-mount technology (SMT) factory, and demands additional capital equipment, floor space, cycle time, and headcount. An alternate approach to traditional capillary underfill is wafer-applied underfill. The underfill is applied after wafer bumping and sawing, but prior to the picking of the individual die from the saw tape. This paper describes the coating and assembly processes. Liquid-to-liquid thermal cycle shock tests (-55 to +125/spl deg/C) have been performed on test vehicles assembled with the wafer-applied underfill. First failures were at over 1000 cycles. Weibull plots of the data and failure analysis are presented.     

An optimization study of underfill dispensing volume

The underfill dispensing volume has been modeled and verified through both experiments and application of statistical technique. The model established is capable of estimating the operating range of the dispensing volume of a defined flip chip assembly and is targeted to reduce wastage as well whilst fulfilling the reliability requirement. The model has taken into consideration the reliability factor, e.g., presence of fillet; manufacturing tolerance of bumps size and standoff variation. In this study, the actual volume for flip chip assemblies prepared in a controlled manner, so that fillets were seen on all sides, was compared with the recommended underfill volume. It was found that the model tended to yield a higher volume and it is concluded that this variation is related to the over estimation of the fillet element in the formulation. For reliability assessment, these flip chip assemblies were examined under C-mode SAM and no voids were found. These flip chip assemblies also passed electrical testing after 500 cycles of air to air thermal cycles and therefore are proven to meet the reliability requirement.     

The effects of rheological and wetting properties on underfill filler settling and flow voids in flip chip packages

As the bump diameter and bump pitch of flip chip packages get smaller, the underfill becomes more resistant to flow. Therefore, low viscosity underfills are used in the process to increase the throughput. Problems associated with low viscosity underfills include filler settling and flow induced voids due to fast edge flow. In this paper, we will discuss how the rheological properties can affect underfill filler settling and flow voids. The effects of yield stress of underfill on filler settling and the effects of shear thickening of underfill at large shear rates on flow voids of underfill were investigated. It was shown that the underfills with small fillers have shear-thickening viscosity and yield stress. The filler settling of underfills with yield stress was greatly reduced. A video underfill flow metrology with quartz die packages was developed for flow void observation. The correlation between underfill, substrate properties, and flow voids formation based on the video underfill flow measurement will be discussed.     

Reliability issues of low-cost overmolded flip-chip packages

A significant need exists for the determination of critical stress characteristics within the low-cost overmolded flip-chip (OM-FC) packages. A systematic stress analysis is reported to investigate the OM-FC package for the optimal design of package geometries, materials combinations during the attachment, and thermal testing processes. A parametric study is conducted seeking the best package performance during the identified most stringent process which causes the largest stress within the low-cost substrate. High-stress location is predicted by finite-element analysis, and it was found that mold compound (MC) curing is the most stringent process for the reliability of substrate; higher underfill fillet, thicker die, larger die size without causing edge effect, solder mask defined structure resulted in smaller stresses in substrate. MC with lower coefficient of thermal expansion is a preferable and compliant substance that is good for using as molding and underfill material     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Underfill selection methodology for fine pitch Cu/low-k FCBGA packages

A systematic underfill selection approach has been presented to characterize and identify suitable underfill encapsulants for large size flip chip ball grid array (FCBGA) packages. In the selection scheme, a total of six evaluation factors such as fracture toughness, coefficient of moisture expansion, flowability, delamination performance and filler settlement were considered. Driving stresses for package failure were also included as a factor of consideration, which clearly depends on the package size and geometry. Based on the approach adopted, underfill material that is suitable for 35 × 35 mm² packages with 15 mm die size and 45 × 45 mm² packages with 21 mm die size was selected. Target value for underfill properties has also been revised.