基于FPGA的H.264解码IP核中CAVLC熵解码模块的设计

提出了一种基于FPGA的H.264视频解码的IP核设计方案,对以NIOS Ⅱ软件处理器为内核的SOPC系统进行了优化,对CAVLC熵解码进行了优化。CAVLC熵解码模块硬件加速的方法,与无硬件加速的NIOS Ⅱ软件解码方法相比,缩短了解码耗时,使基于FPGA的H.264视频实时解码和播放成为可能。     

H.264硬件解码核的FPGA实现

针对H.264/AVC的视频解码问题进行了研究,给出了H.264解码核的硬件实现方案,对熵解码CAVLC查表方案进行了优化.详细介绍了句法预测模块、反量化、逆DCT以及帧内预测模块的具体实现结构;并引入流水线、并行处理和状态机处理方法来提高处理速度,实现了解码结构上的优化.该算法在EP2S60F672C5ES FPGA上获得验证,结果表明给出的H.264解码算法是正确的,且有节省硬件资源和较快解码速度的优点.     

AVS熵解码与DSP实现

阐述了AVS标准的进展情况及AVS标准的特点,重点介绍了AVS熵解码的原理和采用Equator公司MAP-CABSP-15处理器中的协处理器(Vlx)实现AVS熵解码的方法.     

基于FPGA的AVS熵解码模块的设计与实现

提出了一种适用于AVS的熵解码模块的VKSI实现方案。针对解码速度、实现复杂度及系统模块间的协作问题，给出了一种减少解码时间和系统资源占用的硬件实现方法。     

一种新型的AVS熵解码码表结构

传统AVS熵解码过程中需要存储大量的码表数据,并且在码表查询和切换的过程中存在很多的判断和跳转指令,严重地降低了解码速度,不利于DSP的实现。为了实现嵌入式AVS视频解码器,通过分析熵解码码表的特点,提出了一种新型的码表结构和一种分组查询的查询方法,代码实现采用DSP汇编语言。结果表明,与传统的码表结构和查询方式相比较,大大节省了数据空间,缩短了代码的执行时间,提高了解码的效率。     

基于码头分组的H.264变长解码算法优化

H.264标准在编解码模块定义了一种基于内容的变长编码(CAVLC),对于实时处理来说,若该部分计算量过大,将影响整个系统的处理速度。对H.264熵解码模块进行了研究,在分析了CAVLC码表特征后,利用分组优化查表思想,提出了码头分组的快速变长熵解码方法。结果表明该方法使得H.264解码器在熵解码模块质量没有下降的情况下,速度提高了4倍以上。     

AVS中可变长解码器的硬件设计

AVS是我国自主制定的音视频编码技术标准。简要介绍AVS标准视频压缩部分的特点,重点研究AVS可变长熵解码的原理和技术方法并进行优化,主要采用并行解码结构以达到实时解码。在此基础上提出了一种针对AVS视频编码标准的变长码——指数哥伦布码解码的硬件设计结构,最后给出实现该硬件结构对应FPGA实验仿真结果。     

H.264视频解码器的ASIC实现及其中的熵解码

H.264标准是具有极高压缩率、较强的抗误码特性、开放的性质的最新国际标准.开展对其相关领域的研究无论是在知识产权方面还是在经济效率方面,都有很重要的意义.其中熵解码部分是很重要,也是很难于解决的部分.本文仅对熵解码中的Exp_golomb（Exponential Golomb）部分做一介绍,并给出一种硬件实现方法.     

基于码头分组的CAVLC解码算法优化

H.264的变长编码(CAVLC)针对不同的编码系数采用多组码表分别进行编码,在提高熵编码效率的同时增加了解码算法的复杂度.本文在分析R.Hashemian定长分组多级查找表解码方法的基础上,结合码表的结构特点和统计规律,提出了一种基于码头分组的CAVLC解码优化算法.结果表明,基于码头分组的CAVLC解码优化方法解码速度优于R.Hashemian法,同时节省了24.7%的存储空间.     

H.264 CABAC加速器的设计

H.264主要档次采用的CABAC熵编码技术在提高视频压缩比率的同时,严重增加了编/解码的计算复杂度,嵌入式系统由于其低成本低功耗的要求,需要专用硬件加速器来进行CABAC编/解码。设计了一个高性能H.264 CABAC硬件加速器,该加速器可配置为编码或解码模式,高效地实现CABAC编/解码操作。通过性能评估实验,在220 MHz时钟频率下,该加速器能够实现平均147 Mbps(1.5 cycle/bit)的编码速度和220 Mbps(1 cycle/bit)的解码速度。与软件实现相比,加速器获得50倍以上的性能提升。     

Sequential decoding with ARQ and code combining: a robust hybridFEC/ARQ system

Sequential decoding with ARQ (automatic-repeat-request) and code combining under the timeout condition is considered. That is, whenever the decoding time of a given packet exceeds some predetermined duration, decoding is stopped and retransmission of the packet is requested. However, the unsuccessful packets are not discarded, but are combined with their retransmitted copies. It is shown that the use of code combining allows sequential decoding to operate efficiently even when the coding rate R exceeds the computational cutoff rate R _comp. Furthermore, an analysis of the selective-repeat ARQ scheme shows that the use of code combining yields a significant throughput even at very high channel error rates, thus making the system very robust under severe degradations of the channel     

一种改进的CAVLC分组解码优化算法

CAVLC（基于上下文的自适应变长编码）由于码字的长度不固定,其解码器的设计往往是整个视频解码器的难点之一。文中对H．264熵解码模块进行了研究,利用分组优化查表思想,在分析了CAVLC码表特征后,提出了一种将CAVLC码字分为前缀和后缀两部分,根据前缀分组,利用后缀信息查表得到对应比特串的分组解码优化方法。结果表明,所提出的CAVLC分组解码优化算法在节省存储空间和提高解码速度方面具有优异的性能。     

A Reed-Solomon coded DS-CDMA system using noncoherent M-aryorthogonal modulation over multipath fading channels

The performance of Reed-Solomon (RS) coded direct-sequence code division multiple-access (DS-CDMA) systems using noncoherent M-ary orthogonal modulation is investigated over multipath Rayleigh fading channels. Diversity reception techniques with equal gain combining (EGC) or selection combining (SC) are invoked and the related performance is evaluated for both uncoded and coded DS-CDMA systems. “Errors-and-erasures” decoding is considered, where the erasures are based on Viterbi's (1982) so-called ratio threshold test (RTT). The probability density functions (PDF) of the ratio associated with the RTT conditioned on both the correct detection and erroneous detection of the M-ary signals are derived. These PDFs are then used for computing the codeword decoding error probability of the RS coded DS-CDMA system using “errors-and-erasures” decoding. Furthermore, the performance of the “errors-and-erasures” decoding technique employing the RTT is compared to that of “error-correction-only” decoding refraining from using side-information over multipath Rayleigh fading channels. As expected, the numerical results show that when using “errors-and-erasures” decoding, RS codes of a given code rate can achieve a higher coding gain than without erasure information     

基于分段循环冗余校验的极化码自适应连续取消列表译码算法

针对极化码连续取消列表(SCL)译码算法为获取较好性能而采用较多的保留路径数,导致译码复杂度较高的缺点,自适应SCL译码算法虽然在高信噪比下降低了一定的计算量,却带来了较高的译码延时。根据极化码的顺序译码结构,该文提出了一种分段循环冗余校验(CRC)与自适应选择保留路径数量相结合的SCL译码算法。仿真结果表明,与传统CRC辅助SCL译码算法、自适应SCL译码算法相比,该算法在码率R=0.5时,低信噪比下(–1 dB)复杂度降低了约21.6%,在高信噪比下(3 dB)复杂度降低了约64%,同时获得较好的译码性能。     

结合6-QAM和双层LDPC码的编码调制研究

针对阶数为3 ×2p的非标准调制与纠错编码难以匹配的问题,提出了一种面向6阶正交幅度调制(QAM)的双层编码调制传输方案.在发送端,采用有限域GF(2)低密度奇偶校验(LDPC)码与GF(3)LDPC码进行分层编码,并将两种编码码字映射为6进制码字后进行6-QAM调制;在接收端,根据GF(2) LDPC码和GF(3) ...     

Sequential decoding with an efficient partial retransmission ARQstrategy

The authors present and analyze an efficient partial retransmission automatic repeat request (ARQ) strategy using convolutional coding and sequential decoding in conjunction with code combining. In the proposed ARQ scheme, whenever a packet of data needs to be retransmitted that packet is not repeated entirely as in the case of conventional full retransmission ARQ strategies. Instead, symbols of that packet are repeated a few at a time, sequentially, as needed, hence making a more effective use of the channel. It is shown that partial repetitions and code combining still yields an increase of the apparent Pareto exponent of sequential decoding, as in the case of full repetition-code combining. A throughput analysis shows that the partial retransmission ARQ strategy yields a substantial throughput improvement over the full retransmission-code combining ARQ strategies     

On the construction of a class of majority-logic decodable codes

The attractiveness of majority-logic decoding is its simple implementation. Several classes of majority-logic decodable block codes have been discovered for the past two decades. In this paper, a method of constructing a new class of majority-logic decodable block codes is presented. Each code in this class is formed by combining majority-logic decodable codes of shorter lengths. A procedure for orthogonalizing codes of this class is formulated. For each code, a lower bound on the number of correctable errors with majority-logic decoding is obtained. An upper bound on the number of orthogonalization steps for decoding each code is derived. Several majority-logic decodable codes that have more information digits than the Reed-Muller codes of the same length and the same minimum distance are found. Some results presented in this paper are extensions of the results of Lin and Weldon [11] and Gore [12] on the majority-logic decoding of direct product codes.     

Trellis based code combining protocols for Reed-Muller codes

A novel code combining system based on Reed-Muller codes is presented. Because of their simple structure RM codes are simple to decode using a trellis based soft maximum likelihood decoder (SMLD). The decoder exploits the modular structure of the RM code to construct a set of nested trellises which minimise the complexity of the decoder by re-using the results of previous decoding attempts. A protocol utilising this technique to produce an efficient code combining ARQ-scheme is also introduced