Adaptive-biased buffer with low input capacitance

A new analogue buffer, which is a differential-pair-based level shifter followed by an adaptive-biased cascode source follower, is proposed. The structure exhibits low input capacitances, enhanced slew rate, high bandwidth and low distortion. The simulated results have shown input capacitance of 99.5 fF at 1 MHz, slew rate of 55.5 V/μs, -3 dB bandwidth of 37.9 MHz, and THD less than 1% for 1 Vpp input signal up to 6 MHz at a 100 kΩ//15 pF load. The buffer consumes 2.4 mW at 5 V supply in a 0.8 μm n-well CMOS technology     

Wideband CMOS current conveyor

A novel CMOS second generation current conveyor (CCII) for high frequency current-mode signal processing is described. The input stage consists of a regulated current cell coupled to a source follower, and the output stage is a cascode current mirror. This architecture provides the high input/output conductance ratio for current transfer. Simulations show that a 3 dB bandwidth extends beyond 100 MHz     

Process corner detection by skew inverters for 500 MHZ 2×VDD output buffer using 40-nm CMOS technology

A PVT detection and compensation technique is proposed to automatically adjust the slew rate of a high-speed 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output signal is adaptive. The proposed design is implemented using a typical 40 nm CMOS process to justify the slew rate compensation performance. By on-silicon measurements, the data rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load. Particularly, the maximum slew rate improvement is 8%, the core area of the proposed design is 0.052×0.254 mm², the maximum slew rate is 0.53 (V/ns), and the area overhead is only 31% for one single output buffer.     

A 1.2-μm BiCMOS sample-and-hold circuit with aconstant-impedance, slew-enhanced sampling gate

A new sampling gate circuit, with dual outputs functioning alternately in the track and hold modes, is integrated in an open-loop sample-and-hold circuit architecture achieving greater than 450-MHz small-signal input bandwidth and 100-MHz maximum sample rate. The sampling gate also incorporates slew enhancement techniques to achieve (+430 V/μs, -510 V/μs) slew rate and features a `built-in' buffer to maintain constant input impedance for both the track and hold modes, simplifying design of the front-end input buffer. Special on-chip clock generation circuits are used to minimize sampled pedestal (+4 mV). Power dissipation is less than 300 mW, including output driver. Measured harmonics are 58 dB down for a 2 V_p-p 20-MHz sine wave sampled at 100 MHz     

High slew-rate CMOS operational amplifier

A 0.8 /spl mu/m CMOS operational amplifier configuration with a slew rate in excess of 2 V/ns and a unity gain bandwidth of 55 MHz with a load capacitance of 15 pF is proposed. This employs a dynamic technique that turns on a large current source when the rate of change of input is larger than a pre-decided value.     

A novel low power flip-flop design using footless scheme

A highly compact source follower coupling based low-pass filter (LPF) topology is proposed that synthesizes a 3rd-order low-pass transfer function in a single stage with no use of operational amplifiers. Chopper stabilization technique is utilized to reduce 1/f noise for minimizing the in-band integrated noise. Implemented and simulated in a 0.18 μm CMOS process, the 3rd-order LPF achieves a ??3 dB bandwidth of 20 MHz with a 280 μA total current from a 1.4 V supply voltage, defining a power-per-pole/bandwidth efficiency of 6.5 μW/MHz. The output noise density at low frequencies is largely reduced with chopper stabilization technique. The integrated output noise from 10 kHz to 2 MHz is minimized from 22.47 to 7.04 μV_rms, with a 10.1 dB improvement. The averaged output noise density over the filter bandwidth is 9.4 nV/√Hz, which is mostly contributed by thermal noise of transistors.     

A wide-band, low-power, high slew rate voltage-feedback operationalamplifier

A wide-band low-power voltage-feedback operational amplifier on a 3 GHz, 40 V complementary bipolar technology is described. The class AB input stage takes advantage of some current-boost transistors which enhance and linearize the slew-rate during large-signal operation without increasing the power consumption. The triple-buffered output stage provides 100 mA of load current maintaining good linearity. Since the circuit design and technology development were concurrent, several different circuits were stepped into one wafer to fully characterize the process and identify the best product candidates. The low-current version of this chip has a quiescent current of 2.5 mA, 2000 V/μs slew rate and gain bandwidth of 110 MHz. The medium-current version draws only 6.5 mA of current at the same supply voltage while the slew rate increases to 3500 V/μs and bandwidth to 210 MHz. Both parts are operational from +/-2.75 V to +/-18 V supply range. Die size is 51 mils by 76 mils on a poly-emitter CB process     

A 1-V BiCMOS rail-to-rail amplifier with n-channel depletion modeinput stage

A BiCMOS rail-to-rail operational amplifier capable of operating from supply voltages as low as 1 V is presented. The folded cascode input stage uses an nMOS depletion mode differential pair to provide rail-to-rail common mode voltage range while typically requiring only 40 fA of input bias current. The bipolar transistor differential-to-single-ended conversion network employs a low-voltage base current cancellation technique which provides high input stage voltage gain from a l-V supply yet allows a 3-V/μs slew rate capability. The bipolar transistor output stage uses a low-voltage translinear loop which maintains a low impedance signal path to the output common emitter power devices. This circuit topology enables the amplifier to achieve a 4-MHz bandwidth with 60° of phase margin. The output voltage can swing to within 50 mV of each supply rail. An “on-demand” base current boost technique will be presented which can provide up to 50 mA of output drive capability from a 5-V supply, yet consumes only a few microamps when the output is in the quiescent state. A low voltage level shift technique will be described which uses an n-channel depletion mode source follower to provide isolation between the input and output stages     

低压工作的轨到轨输入／输出缓冲级放大器

本文提出了一种低压工作的轨到轨输入／输出缓冲级放大器。利用电阻产生的输入共模电平移动,该放大器可以在低于传统轨到轨输入级所限制的最小电压下工作,并在整个输入共模电压范围内获得恒定的输入跨导;它的输出级由电流镜驱动,实现了轨到轨电压输出,具有较强的负载驱动能力。该放大器在CSMCO．6-μmCMOS数模混合工艺下进行了HSPICE仿真和流片测试,结果表明：当供电电压为5V,偏置电流为60uA,负载电容为10pF时,开环增益为87．7dB,功耗为579uw,单位增益带宽为3．3MHz;当该放大器作为缓冲级时,输入3VPP10kHz正弦信号,总谐波失真THD为53．2dB。     

A 90-nm CMOS 800 MHz 2$$\times$$VDD output buffer with leakage detection and output current self-adjustment

This work presents a 800 MHz 2\(\times\)VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted by Delay buffer and the leakage current sensor which compensates the dynamic and static currents, respectively. Most important of all, a deterministic sizing optimization method for the output transistors is reported and analyzed. The proposed design realized using a typical 90 nm CMOS process shows that the maximum data rate is 450/800 MHz given supply voltage 1.0/1.8 V with PCB and SMA connectors . The SR variation is reduced over 43% after the compensation of the leakage detection. The core area of the prototype is 0.056 \(\times\) 0.439 mm\(^2\), and the power consumption is 68.9/98.5 (\(\upmu\)W/MHz) at 450/800 MHz, respectively.     

A tiny, high-speed, wide-band, voltage-feedback amplifier stablewith all capacitive load

A tiny, high-speed, wide-band, voltage-feedback operational amplifier capable of driving unlimited capacitive load is described. A class AB input stage is combined with a modified dynamic Witch-Hazel current mirror to provide high slew rate and wide bandwidth with a small die area and small idle current. An RC network couples part of the capacitive load into the high-impedance node, therefore lowering the dominant pole and increasing stability as a function of capacitive load. The part was fabricated on a 3 GHz, 40 V complementary bipolar process. The quiescent current of the chip is 4.5 mA with 1500 V/μm slew rate and a -3 dB bandwidth of 235 MHz. The part is operational from ±2.5 V to ±18 V supply range. Die size is 38 mils by 46 mils and it fits into a tiny surface outline transistor (SOT) package     

High-gain,high-bandwidth,rail-to-rail,constant-gm CMOS operational amplifier

This study presents a high-gain, high-bandwidth, constant-g_m , rail-to-rail operational amplifier (op-amp). The constant transconductance is improved with a source-to-bulk bias control of an input pair. A source degeneration scheme is also adapted to the output stage for receiving wide input range without degradation of the gain. Additionally, several compensation schemes are employed to enhance the stability. A test chip is fabricated in a 0.18?µm complementary metal-oxide semiconductor process. The active area of the op-amp is 181?×?173?µm² and it consumes a power of 2.41?mW at a supply voltage of 1.8?V. The op-amp achieves a dc gain of 94.3?dB and a bandwidth of 45?MHz when the output capacitive load is connected to an effective load of 42.5?pF. A class-AB output stage combining a slew rate (SR) boost circuit provides a sinking current of 6?mA and an SR of 17?V/µs.     

一种高性能CMOS运算放大器的设计

采用Chartered0.35μm工艺,设计了一种开环增益为84dB,-3dB带宽达12kHz,转换速率为400V/μs,相位裕度为60°的高性能运算放大器。其中,通过两级放大器级联的套筒式运放结构的设计,解决了高增益和大输出摆幅的需要;同时,采用带隙电流源作偏置电路,保证了运算放大器的设计精度。     

Low‐Noise MEMS Microphone Readout Integrated Circuit Using Positive Feedback Signal Amplification

A low‐noise readout integrated circuit (ROIC) for a microelectromechanical systems (MEMS) microphone is presented in this paper. A positive feedback signal amplification technique is applied at the front‐end of the ROIC to minimize the effect of the output buffer noise. A feedback scheme in the source follower prevents degradation of the noise performance caused by both the noise of the input reference current and the noise of the power supply. A voltage booster adopts noise filters to cut out the noise of the sensor bias voltage. The prototype ROIC achieves an input referred noise (A‐weighted) of ?114.2 dBV over an audio bandwidth of 20 Hz to 20 kHz with a 136 μA current consumption. The chip is occupied with an active area of 0.35 mm² and a chip area of 0.54 mm².     

Class-AB Fully Differential Voltage Followers

Two fully differential class-AB voltage followers with essentially enhanced slew rate are introduced. The first one is based on the crossquad cell. The second one is based on the conventional voltage follower. Class-AB operation with accurate control of the quiescent current and extended bandwidth is achieved in both cases with minimal additional circuitry, zero extra static power dissipation and without increasing supply requirements. Experimental results of a test chip fabricated in 0.5- CMOS technology show slew rate enhancement of over a factor 15 and large extension of the peak-to-peak input range.     

A multistage amplifier technique with embedded frequencycompensation

A new multistage operational amplifier topology requires only N-2 embedded compensation networks for N gain stages. The compensation circuits do not load the output stage, and noninverting gain stages are not required as in previous multistage approaches. Consequently, high gain, wide bandwidth, fast slewing, and excellent power efficiency are achieved. A low-power resistance-capacitance compensation technique assures stability and fast settling over process, voltage, and temperature variations. Implemented in a 0.6-μm n-well CMOS process, a single ended three-stage prototype dissipates 6.9 mW at 3.0 V with 102 dB gain, 47 MHz bandwidth, and 69 V/μs average slew rate with 40 pF load     

Self-biased cross-coupled low-cost fully-differential CMOS operational amplifier

A low-cost fully-differential operational amplifier (opamp) using a novel self-biased cascode output stage and cross-coupled input stage is proposed. Fabricated in only an 84/spl times/67 /spl mu/m/sup 2/ area with TSMC 0.35 /spl mu/m technology, and loaded with more than 100 pF capacitance, the opamp possesses 60 dB DC gain, 3 V//spl mu/s slew rate, 7.8 MHz unity-gain bandwidth, and -48 dB total harmonic distortion.     

Low-power high-slew-rate CMOS buffer amplifier for flat panel display drivers

A new high-slew-rate CMOS buffer amplifier consuming a very small quiescent current is proposed. This buffer amplifier recursively copies the output driving current and increases the tail current of the input differential pair during slewing. Since the proposed buffer has a possible slew rate higher than 10 V//spl mu/s for a load capacitance of 1 nF almost independently of static currents as low as 1 /spl mu/A, this buffer amplifier is promising for column driver ICs of flat panel displays that require low static power consumption, high current driving capabilities, and small silicon areas.     

一种集成低压低功耗电流复制电路设计

本文提出了一种集成低压低功耗电流复制电路。利用单级放大器和电压跟随器构成的负反馈回路实现对输入电压跟的跟随,利用等比例电阻实现电流的等比例复制,电路结构简单,仅由5个MOS管和2个等比例电阻构成。基于TSMC 0.18μm工艺完成电路设计,使Spectre完成电路仿真。结果表明,电路电源电压为1V时,电路静态功耗仅为1μW。在输入电流范围为0-50μA时,输出电流线性跟随输入电流,当输入电流大于3μA时,电流复制精度大于99%,电路带宽为31MHz。     

High Slew-Rate and Very-Low Output Resistance Class-AB Flipped Voltage Follower Cell for Low-Voltage Low-Power Analog Circuits

Wireless Personal Communications - A low output resistance and high slew rate class-AB flipped voltage follower (FVF) cell is presented in this paper. The proposed FVF cell consists of cascoding...