CAD／CAE／CAM在车身工装模具中的应用

ＣＡＤ／ＣＡＥ／ＣＡＭ在车身工装模具中的应用一汽集团公司模具中心郭佩英，卢金火，张建国国内外汽车工业的飞速发展，推动着车身工装模具行业的进步。为提高车装模具的制造精度，缩短生产周期，降低成本，在生产过程中主要进行两方面工作：一是加速研究工装模具的新结...     

注塑模CAD／CAM系统

本文是介绍我厂在工厂技术改造中采用先进的注塑模ＣＡＤ／ＣＡＭ一体化系统，武装模具生产的总结材料。     

模具CAD／CAM中的DNC技术

本文从硬件联接、后置处理数据文件的生成及网络通信软件的编制等三个方面，介绍了模具ＣＡＤ／ＣＡＭ中如何实现ＤＮＣ技术。     

快速光造型技术的现状与展望

快速光造型以新颖的“叠加”成型法取代传统的“去除”成型法，综合运用了激光、高分子材料、模具ＣＡＤ／ＣＡＭ及自动控制等多学科技术，可以一次成型制造出任意复杂形体的高精度模具，而无需任何机械加工。这是一项具有跨世纪意义的新技术，在未来的国民经济诸多领域中必将得到广泛应用。     

基于CADDS5／DDM软件的冷冲模CAD系统

本文针对ＣＡＤＤＳ５／ＤＤＭ软件的特点，分析了冷冲模的设计特点与软件现状，结合模具设计师的实际需要和应用特点，就冷冲模ＣＡＤ系统中应用ＣＡＤ技术进行简要的论述和分析。系统以ＣＡＤＤＳ５／ＤＤＭ为软件平台，采用分布式的ＣＡＤ系统结构，使用图形菜单与文字菜单相结合的人机对话方式，特别对这套ＣＡＤ系统的实用性进行了论述。     

激光熔覆高温合金及其应用

高温工模具的失效方式主要为工作面的热磨损和氧化热疲劳。针对这一特点，选用镍基高温合金＋ＷＣ和ＭＣｒＡＩＹ合金（Ｍ＝Ｎｉ，Ｃｏ）＋ＷＣ进行激光熔覆试验，并对激光熔覆层进行组织性能测试。结果表明，镍基高温合金＋ＷＣ有较高的热强性，而ＭＣｒＡＩＹ＋ＷＣ则有较佳的抗氧化性。将两类合金激光熔覆层应用于无缝钢管顶头上提高使用寿命１～４倍。其中以ＭＣｒＡＩＹ合金＋１０％ＷＣ激光熔覆顶头寿命最长。     

新型的制造技术—快速成型制造技术

快速成型制造技术是国际上新开发的一基高科技成果。它集成了现代数控技术，ＣＡＤ／ＣＡＭ技术，激光技术和新型的材料科学于一体，突破了传统的机械加工方法，不需要模具或工具，能快速，准确，方便地加工出开头复杂，精度高的零件。     

快速光造型层间叠合特性研究

快速光造型层间叠合特性研究刘玉，鄂茂华，张汉泌（华中理工大学武汉４３００７４）快速光造型是一种新颖的模型制造方法，涉及到激光、高分子材料、ＣＡＤ／ＣＡＭ及数字控制等多种高新技术。其基本原理是：首先在计算机上对待制模型（或模具）进行ＣＡＤ设计，并对设计...     

成型密度对PTCR性能影响的研究

本文系统的研究了成型密度对ＰＴＣＲ各项性能的影响，得到了成型密度不宜过大的结论。并对成型密度对模具寿命的影响，和压片原始分层的原因也进行了分析。     

复杂型面产品与模具的CIMS

ＣＡＤ／ＣＡＭ／ＣＡＥ技术是适应市场需求而兴起的一项新技术。在目前的经济形势下，市场需求和设点加快，新产品的开发和生产周期要尽可能缩短。按照传统的产品生产开发、模具加工生产、产品批量的生产过程，产品周期较长，根本满足不了市场的需求。因而只有对新产品的开发到出厂的环节要素重新组合、创新才能满足要求。笔者在近期的生产调研中发现，国内的某些中小企业基本上仍用传统方法开发新品，而国内外的某些企业纷纷采用新技术、新设备对传统方法进行改进。在众多方案中，面向ＣＩＭＳ集成的ＣＡＤ／ＣＡＭ／ＣＡＥ技术，无疑是一…     

塑料成型模具设计多媒体与动态演示系统的研制

在对塑料成型工艺、成型设备、成型所用模具的特点进行系统分析的基础上，研制开发了旨在对初入模具行业的技术人员以模具设计知识为指导的塑料成型模具设计多媒体与动态演示系统。该系统利用多媒体计算机的文本、图像、动画、视频和音频的综合处理能力和其交互式特点，借助VB、AUTOCAD、3DS MAX等高级软件，为塑料成型模具设计学习人员创造了一个图文并茂、生动逼真的学习环境。     

芯片推力方法与MEMS芯片固化工艺的研究

介绍了封装推力与MEMS(微电子机械系统芯片)固化的通用工艺,提出了芯片固化中遇到的问题.针对异议的工艺与材料进行了试验,采用数理统计方法进行了分析.对MEMS装片材料与结构进行研究,找出芯片推力实施的过程的问题,实施优化MEMS芯片推力方法.最终采用数理统计方法验证了该推力方法在工艺实施过程的可行性,该方法满足了大生...     

粘片机中芯片丢失的光敏检测方法及其分析

论述了粘片机中芯片丢失的检测方法,采用红外发光二极管和硅光敏晶体管,实现了芯片丢失的快速、准确的检测。     

多层芯片应用中的封装挑战和解决方案

The continuous growth of stacked die packages is resulting from the technology‘s ability to effectively increase the functionality and capacity of electronic devices within the same footprint as a single chip.The increased utilization of stacked die packages in cell phone and other consumer products drives technologies that enable multiple die stacks within a given package dimension.This paper reviews t6he technology requirements and challenges for stacked die packages.Foremost among these is meeting package height is 1.2mm for a single die package.For stacked die packages,two or more die need to fit in the same area.That means every dimension in the package has to decrease,including the die thickness.the mold cap thickness,the bond line thickness and the wire bond loop profile.The technology enablers for stacked die packages include wafer thinning,thin die attachment,low profile wire bonding,bonding to unsupported edges and low sweep molding.     

Fabrication of Precise Die Edges for Micro-Optical and MEMS Applications

A method for fabricating precise silicon die edges aligned to a precision of 0.5 mum to the features on the front side of the die without damaging these features is described in this paper. A two step die edge fabrication process with die edge defined by silicon DRIE on the front side of the die and edge grinding on the backside of the die was developed. The features on the front-side of the die close to the edge are not mechanically damaged by this technique. Test structure design and fabrication to measure the precision of die edge with respect to the features on the front side is discussed. Die cleaning process using a protective coating deposited prior to the sawing and grinding processes is also presented.     

Die cracking and reliable die design for flip-chip assemblies

Die cracking during underfill cure or thermal cycling is a cause for concern in flip-chip assemblies. In this work, an integrated process-reliability modeling methodology has been developed to determine the stresses at the backside of the die during underfill cure and subsequent thermal cycling. The predicted die stresses have been compared with experimental data, and excellent agreement is seen between the theoretical predictions and the experimental data. The modeling methodology has been used to understand the effect of material and geometry parameters such as substrate thickness, die thickness, standoff height, interconnect pitch, underfill modulus and coefficient of thermal expansion (CTE), and solder mask CTE on die stresses and thus die cracking. Based on underfill-cure and thermal cycling models for specific cases, the critical flaw size to induce catastrophic die cracking has been calculated using linear-elastic fracture mechanics. Design recommendations, including die thinning and polishing, have been made to reduce the tensile stresses on the backside of the die and thus die cracking     

定子片精密冲模阴阳模粘接结构破坏的修复技术

定子片精密冲模在设计和工艺制造上的不适当，以致造成阴阳模粘接结构发自下而上这重新确定应用环氧型结构胶，粘接工艺和修改冲模粘接结构，完好地修复冲模，冲制出的定子片性能达到技术要求。     

DB-6120全自动芯片键合机图像处理系统分析及软件处理

概述了DB-6120全自动芯片键合机图像处理系统的组成及工作原理,重点介绍了软件结构及设计方法,并对晶片及芯片对准、芯片识别技术进行了重点探讨。     

Package design and materials selection optimization for overmolded flip chip packaging

In overmolded flip chip (OM-FC) packaging, interface delamination-particularly at the die/underfill interface-is often expected to be a main type of failure mode. In this paper, a systematic stress analysis is performed by means of numerical simulations for the optimal design of package geometries and materials combinations. The behavior of the interfacial stresses at the die/underfill and die/mold-compound (MC) during the molding process is investigated, followed by a parametric study to examine the effects of the package geometries and materials parameters including the underfill fillet size, die thickness, die size, die standoff height, solder mask design pattern, MC used as underfill material, MC properties, etc., on the interfacial stresses. The results demonstrate that a proper selection of these parameters can mitigate the interfacial stresses, and thus is important for the reliability of the low-cost OM-FC packages.     

Evaluation of the impact of the physical dimensions and material of the semiconductor chip on the reliability of Sn3.5Ag solder interconnect in power electronic module: A finite element analysis perspective

This paper primarily focuses on an evaluation study for the temperature cycling capability of tin silver solder interconnect in power electronic applications by the impact of die dimensions and die material properties. The study was investigated on finite element analysis perspective on chip/solder/substrate structure. A commercially available chip was chosen in the finite element analysis (FEA) as the nominal base die. Two thermal cycle profiles were utilised. The effect of die area, die thickness and material properties (Si and SiC) on the thermal cycling capability of the solder layer was investigated from FEA perspective. From the FEA, it was concluded that decrease in die thickness resulting in increment of thermal cycling capability of solder layer for both material (Si and SiC). Increase in die area increases the thermal cycling capability of solder. For higher ΔT thermal cycle, solder under SiC die perform better than solder under Si die in terms of thermal cycling capability. When the die thickness become smaller than a threshold value of the thermal cycle regime, solder under Si die have better thermal cycling capability than solder under SiC die. Additionally a parametric study was undertaken for a SiC chip/substrate structure under high ∆ T temperature cycling profile for solder layer geometric parameter (wetting angle, titling angle and thickness). From the parametric study which utilised design of experiments (DoE), a wavelet radial basis surrogate model was generated. A sensitivity analysis was performed on surrogate model in order to identify the most influencing parameter. From the sensitivity analysis, it was concluded that wetting angle and solder layer thickness of solder layer have significant impact on the thermal cycling capability of the solder layer.