The field-assisted turn-off thyristor: a regenerative device withvoltage-controlled turn-off

A solid-state switching element, the field-assisted turn-off (FATO) thyristor, has been developed. This is a regenerative device, which implies that it is capable of carrying very large current densities, with a very small forward voltage drop when it is in its on-state. Most regenerative devices cannot be turned off with a control signal; however, the structure of the FATO thyristor allows it to be switched off by applying a voltage to a high impedance, insulated-gate terminal. This device can also be fabricated with an insulated-gate turn-on structure, so that it is fully switchable using only low-current control signals. The design, fabrication, and characterization of the FATO thyristor are described     

The development of a gate assisted turn-off thyristor for use in high frequency applications

The development of a. high power, high frequency, inverter thyristor is described.

The techniques and procedures used to achieve forward blocking recovery times of less than 2 microseconds are summarized, and electrical test data are included to show that other thyristor Parameters are not too adversely impaired.     

Numerical analysis of turn-off characteristics for a gate turn-off thyristor with a shorted anode emitter

Turn-off current waveform for a gate turn-off thyristor (GTO) with a shorted anode emitter has been calculated numerically by solving the semiconductor basic equations in an equivalent one-dimensional model device. This model is derived from the analysis of current and carrier distributions obtained by a two-dimensional calculation of the on-state of GTO. A calculated turn-off current waveform agrees well with the experimental waveform. The computational time of one case is about 2 min. It is shown that this one-dimensional analysis method is useful for the calculation of the turn-off time. Using this one-dimensional model during the turn-off process and the two-dimensional model in the on-state, the relation between turn-off time and the forward voltage drop can be obtained in relation to the shorted emitter structure. It is shown that the shorted emitter structure is useful to improve this tradeoff relation.     

Induction cooking unit using a gate turn-off thyristor

This paper deals with the design and construction of a 500W 60kHz induction cooking power supply. The novel aspect of the unit is its use of a gate turn-off thyristor (GTO) in a resonant circuit topology, i.e. a Class E circuit.     

Numerical modeling of gate turn-off thyristor using SICOS

A numerical model of gate turn-off thyristors (GTOs) is presented. The concept of a controlled switch realized by a controlled current source is first introduced. Using this basic model, an equivalent circuit for the GTO is given. Using the GTO characteristics given by manufacturers, the equations connected with all the parameters of the equivalent circuit are deduced, and all of the parameters are determined. A sample study is presented. Simulation of this numerical model with the SICOS program gave results in accordance with the experiment     

Description of a technique for the reduction of thyristor turn-off time

A thyristor structure is provided with an anode-gate electrode which is used to speed up the device recovery and reduce its turn-off time. The turn-off process of the anode-gate thyristor is analyzed qualitatively using the charge control approach. Experimental device structures are described and the results of measurements are reported.     

2500-V 600-a gate turn-off thyristor (GTO)

GTO self-turn-off capability provides an advantage over an ordinary thyistor, because of forced commutation circuit removal upon inverter and chopper application, thus substantially reducing equipment size, weight, and mechanical noise. A series of high-power GTO's has been developed, with the present 2500-V-600-A unit as its peak. The most essential design problem for this unit is to establish a principle for increasing maximum gate turn-off current (IATO), while keeping overall thyristor characteristics in reasonable balance. High IATOwas attained by decreasing p-base sheet resistance, as well as decreasing n-emitter finger width. Excellent thyristor characteristics were obtained by adopting a low acceptor concentration near the cathode-gate junction. From a device process point of view, introducing a phosphorus redeposition annealing increased carrier lifetime in the p base to a sufficiently high level. This process contributed most strikingly to improving the off-state voltage.     

A study of design influence on anode-shorted GTO thyristor turn-onand turn-off

Anode-shorted GTO thyristor samples were investigated by means of the free-carrier absorption (FCA) technique. Both the turn-on and turn-off processes were investigated as regards the two-dimensional carrier distribution for different stages of the transient cycles. The results are presented as carrier-map sequences, i.e., 3-D pictures of measured 2-D carrier distributions. Samples were formed as unit segments cut out from large-area devices, and associated with different degrees of anode shorting, silicon thickness, and lifetime treatment. During investigation, the samples were inductively anode loaded, and as regards the turn-off process they were operated near the safe-operation limit. The measurements clearly illustrate the way carriers are transported in the sample when firing the device, and the turn-on process is visualized in steps by means of carrier-map sequences. These measurements are supported by computer simulations. The turn-off process is also visualized in carrier-map sequences measured from two perpendicular directions, and the maps show the critical electric-field expansion which always precedes a turn-off failure due to dynamic breakdown mechanisms. Further on, the effect of design-parameter variations, e.g., anode shorting pattern and carrier lifetime reductions, on destructive GTO turn-off phenomena are discussed     

Microprocessor based simulation and digital logic model of gate turn-off thyristor

A digital logic model of a gate turn-off thyristor is developed considering the turn-on and turn-off mechanisms of the device. A commonly used R-C-D snubber circuit is also included in the proposed model. Relations between different delay times, e.g. storage time, Tall time, turn-off time and tail time, become apparent from the model. The model is simulated with the help of a microprocessor to establish the validity of the proposal.     

Experimental and numerical study of the emitter turn-off thyristor(ETO)

The emitter turn-off thyristor (ETO) is a new family of high power semiconductor devices that is suitable for megawatt power electronics application. ETOs with voltage and current ratings of 4-6 kV and 1-4 kA, have been developed and demonstrated. And those power levels are the highest in silicon power devices and are comparable to those of the gate turn-off thyristor (GTO). Compared to the conventional GTO, the ETO has much shorter storage time, voltage controlled turn-off capability, and much larger reverse biased safe operation area (RBSOA). Furthermore, ETOs have a forward-biased safe operation area (FBSOA) that enables it to control the turn-on di/dt similar to an insulated gate bipolar transistor (IGBT). These combined advantages make the ETO based power system simpler in terms of dv/dt snubber, di/dt snubber, overcurrent protection, resulting in significant savings in the system cost. This paper presents experimental and numerical results that demonstrate the advantages of the ETO     

Numerical simulation of an optoelectronic thyristor in the regime of incomplete turn-off

Direct two-dimensional simulations are used to analyse the possibility of controlling the carrier concentration in the gated base of a GaAs optoelectronic thyristor, which operates in the regime of incomplete turn-off. Modelling results indicate that the number of carriers, light intensity, current distribution, and the position of the light-emitting region the gated base of the thyristor can effectively be changed using gate currents, insufficient to turn the device completely off. The utilization of incomplete turn-off principle can be used for light-intensity modulation and switching purposes.     

Dynamic current localization during turn-off of high-power microgate bipolar switches

The turn-off process of semiconductor switches with distributed microgates in the presence of small embedded technological inhomogeneities of their structure parameters is considered. The process dynamics is studied based on the analytical model of residual plasma displacement and the space charge region dynamics in the base, taking into account ionization in high electric fields. A spatially inhomogeneous switch structure is modeled by two groups of controlled cells with different parameters, i.e., emitter injection efficiencies or carrier lifetimes in n-type bases. Voltage coupling of all cells is complemented by the device interaction with the external circuit. The detrimental effect of current localization at the turn-off stage, which occurs even at a relatively small parameter variance, was studied within the proposed model. The results obtained allow quantitative characterization of the effect of technological inhomogeneities on safe operating area of high-power microgate bipolar switches.     

A study on maximum turn-off current of a high-power GTO

A 6 kV, 6 kA pnpn-type GTO was fabricated and its maximum turn-off current was investigated. The simulation uses a three-segment device model together with an equivalent circuit model. Results of simulations with segments having different on-state voltages showed current concentration in the lower on-state voltage segment in the fall period. By introducing a homogeneous fabrication process, the on-state voltage distribution band was decreased by a factor of 2. The circuit model simulation results showed the maximum peak current of the improved GTO with smaller on-state voltage band was reduced by a factor of 1.33 compared to that of the conventional GTO. A high-power GTO turn-off limiting model was proposed from the measured 6 kA GTO turn-off locus and the segment SOAs. This turn-off limiting model showed that the GTO would be destroyed when the segment current exceeds the SOA at the time a spike voltage occurs in the fall period. It was demonstrated that the maximum turn-off current estimated by this limiting model coincided well with the experimental results     

A new MOS-gated power thyristor structure with turn-off achieved bycontrolling the base resistance

A new MOS-gated power thyristor structure, called the base-resistance-controlled thyristor (BRT), is described. In this structure, the turn-off of a thyristor with an N-drift region is achieved by reducing the resistance of the P-base region under MOS-gate control. In contrast with previous devices, a P-channel MOSFET integrated in the N-drift region is used for this purpose. It has been shown, by two-dimensional numerical simulations and experimental measurements on devices fabricated using a seven-mask process, that devices with 600-V forward blocking capabilities can be achieved with a forward drop close to that for a thyristor. The ability to turn off the thyristor current flow has been verified over a broad range of current densities     

A time- and temperature-dependent 2-D simulation of the GTO thyristor turn-off process

GTO thyristor turn-off process is analyzed for a resistive load case by performing an exact two-dimensional time- and temperature-dependent numerical simulation. A newly defined concept "on-region" is introduced to help understanding of the simulation results. Excess carrier plasma (on-region) in the p-base is squeezed finally to as narrow as 60 µm wide, accompanying a large current density increase at the center of the middle junction. The carriers in the n-base are found not to be greatly affected by the initial plasma squeezing in the p-base. After the on-region width in the p-base reaches its final limit, the excess carriers around the middle junction of the final on-region is rapidly reduced, resulting in complete anode current turn-off.     

A simple energy recovery circuit for high-power inverters with complete turn-on and turn-off snubbers

This paper presents and analyzes an active energy recovery circuit for the inductive turn-on snubber and capacitive turn-off snubber used on high-power gate-turn-off thyristor inverters. The circuit performs as a simple switched-mode power supply and recovers the inductive and capacitive snubbers energy induced in power inverters back into the dc rail with the aid of an extra switch. The features and operation of the proposed circuit are given and supported by PSpice simulations and experimental results.     

Harmonic emission from high-power high-frequency gyrotrons

The results of a study of second-harmonic emission from a gyrotron designed for high-power high-frequency operation at the fundamental of the cyclotron frequency are presented. Stable, very narrow bandwidth second-harmonic cavity emission from 209 GHz to 302 GHz has been observed. An output power of 25 kW and efficiency of 6·5% in the TE_{11, 2, 1}, mode at 241 GHz is reported; this represents the highest power obtained to date from a high-frequency (> 100 GHz) harmonic gyrotron. These experiments have been carried out in a cavity for which the mode density is very high; the cavity diameter is approximately six free-space wavelengths for emission at the second harmonic. Mode competition between fundamental and second-harmonic modes is discussed. It is also shown that, in general, gyrotrons designed for high-power low-Q operation in overmoded cavities at the fundamental will also have high efficiencies and strong emission in second-harmonic modes. Prospects for high-frequency harmonic gyrotrons for plasma diagnostics and other applications are described     

A proposed high-frequency high-power silicon-silicide multilayered device

A new, integrated device, comprised of a series of metal and semiconductor films, is proposed for use as a high-frequency high-power source. The new metal-semiconductor device provides the excess carrier generation and the drift phase angle delay required to accomplish the negative resistance. The metal acts as a reservoir to collect the excess generated carriers from both sides of the semiconductor and to isolate the performance of each element of the integrated device. Following simple scaling rules, the area of an integrated device having n elements is n times larger than the area of each element; and the power output is about n²times the output of a single element at the same operation frequency, if the heat dissipation is not a limiting factor. The device can be fabricated-by using the silicon-silicide epitaxial process with MBE.     

8000-V 1000-A gate turn-off thyristor with low on-state voltage andlow switching loss

An 8 kV, 1 kA gate turn-off thyristor (GTO) that has been designed with a combination of a p-i-n structure and a ringed-anode short structure is discussed. The GTO has been fabricated using a diffusion and epitaxial buffer process. As a consequence, low on-state voltage and low switching loss have been achieved, solving the two major problems in high-voltage GTOs. The device's structure, the p-i-n base process, and the electrical characteristics of the GTO are described     

A new lateral anode switched thyristor (LAST) with currentsaturation and low turn-off time

A novel MOS-gate controlled thyristor, entitled lateral anode switched thyristor (LAST), which exhibits a high current saturation and a low turn-off time, is proposed and successfully fabricated. Experimental results show that the new LAST achieves a current saturation capability larger than 1200 A/cm² even at high anode voltages. The forward voltage drop of LAST is 1.2 V at 100 A/cm ² where 10 V was biased to the dual gates. The turn-off time of LAST without any lifetime-control process is 1.5 μs while that of LAST without p⁺ diverter is about 2.9 μs. Our experimental data indicates that the p⁺ diverter successfully diverts holes in the drift region during the turn-off and a turn-off time is considerably decreased in the proposed LAST. The LAST, where any trouble-some parasitic thyristor mechanism is eliminated, completely suppresses a latch-up and increases the maximum controllable current considerably