一种实时的HDTV解码方案

介绍了一种廉价、低耗、实时的HDTV解码方案，可实时解码比特码率达18--22Mbps的HDTV图像，并通过分析仿真验证了其可行性。     

彩色电视机典型基色矩阵视放电路的理论分析及工程估算

彩色电视机典型基色矩阵视放电路的理论分析及工程估算襄樊大学刘孙刚一、引言目前我国已进入彩电大发展时期，新机型不断出现，影响彩电质量的最后关键电路一基色矩阵视放电路一般采用进口机型，电路参数各有差异，但在工程上如何对各参数进行估算？电路参数改变的依据何...     

HDTV视频解码器输入缓存及系统控制单元的研究

介绍了高清晰度电视（ＨＤＴＶ）视频解码了及系统控制部分的设计与实现，其中包括视频缓存器，音频视频同步控制及显示缓存控制等部分。系统采用现场可编程门阵（ＦＰＧＡ）实现。目前已经研制成功，对我国发展ＨＤＴＶ专用芯片设计具有重要的意义。     

HDTV视频解码器中系统控制功能的实现

本文着重分析ＨＤＴＶ视频解码器中系统控制单元的各关键技术,并给出了一套相应的硬件实现方案。     

先进的数字HDTV视频编码系统的性能分析

先进的数字高清晰度电视是一种全数字式的电视和无线电同时联播的系统，其设计目的是为通过单一的６ＭＨｚ地面广播‘禁忌’频道为广大的覆盖区域提供高质量的ＨＤＴＶ服务。本文阐述了ＡＤ－ＨＤＴＶ视频编码系统的技术细节并提供系统性能的分析。     

HDTV的关键技术

本文讨论高清晰度电视（ＨＤＴＶ）体制的关键技术。本文分析表明，ＨＤＴＶ的关键技术主要包括信源压缩编码、信道编码技术及传输调制技术，而传输调制方式则是ＨＤＴＶ体制的核心内容。     

一种双通道高带宽视频放大器的设计与实现

设计了一种内置75D阻抗匹配器的双通道高带宽视频放大电路。该电路频谱特性宽，在6．5MHz频带内有稳定的增益，单通道放大增益为6dB，每个通道都有箝位功能，电路的两个通道可以串联成增益为12dB的单通道。电路根据国内工艺线而设计，性能已达到国外产品性能水平，制造时所需的掩模版数目比国外产品少，成本低。电路在SIM-BCD的2．0μm 18V Bipolar工艺线上流片，样片经用户测试符合设计要求，可以产业化。     

A Real-Time Video Decoder for Digital HDTV

In this paper, an architecture for real-time digital HDTV video decoding is presented. Our architecture is based on a dual decoding datapath controlled in a fixed schedule with an efficient write-back scheme for anchor pictures. The decoding datapath is synchronized at the block (8 × 8 pixels) level. Unlike other decoding approaches such as the slice bar decoding method and the cross-divide method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. In comparison to data-flow approaches, our method eliminates the complexity associated with tagged data operations. Our anchor picture storage is organized to minimize page-breaks during memory accesses. Simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on an ATSC video format of 1,920 × 1,080 pixels/frame at 30 frames/s, at a bit rate of 18 to 20 Mbps.     

A codec for HDTV signal transmission through terrestrial and satellite digital links

A codec for digital transmission of HDTV is described. The bit-rate compression algorithm is based on advanced techniques such as spatial discrete cosine transform (DCT), temporal differential PCM (DPCM), variable length coding. The codec is designed to operate with both the interlaced studio systems 1125/60 and 1250/50, and, thanks to the inherent flexibility of the packet structure, a wide range of line bit-rates can be used as a compromise between video quality and bit-rate constraints of the digital transmission link. The flexibility of the HDTV codec is highlightened through examples of applications over satellite digital links in practical situations.     

HDTV中显示器件分辨率的探讨

随着电视广播从模拟向数字转移，作为下一代电视的高清晰度电视倍受关注。本文简要论述未来HDTV所用显示器件的分辨率及其制约因素，重点讨论CRT型电视中显示器件分辨率与整机清晰度的关系，分析高分辨率CRT的实现途径。另外，文章也涉及到标准清晰度电视用CRT对分辨率的基本要求。     

PDM: A versatile digital transmission system for video

This report discusses a pulse density modulation (PDM) video transmission system. PDM is a one-bit digital coding scheme with advantages of transparency due to an inherently extended signal bandwidth and relatively simple decoding; these make it ideal for a variety of applications. The system outlined is designed to carry a single analogue video channel, together with several sound channels, over a 140 or 280 Mbit/s digital transmission-link. An alternative option to the sound channels will be to carry a 2.048 Mbit/s data channel. Since the analogue video input will be PDM coded, this will enable the system to carry video formats which have a flat base-band frequency response requirement of in excess of 20 MHz (such as HDTV), allowing a large degree of flexibility in use.     

高清晰度电视芯片中视频和音频同步的异步实现

高清晰度电视的传输流采用了MPEG－2系统层标准ISO／IEC 13818－1。阐述了高清晰度电视（HDTV）传送流中时间信息码在视频和音频同步中的作用,分析了信源解码器中视频和音频同步的原理。就实际芯片中系统时钟的恢复,视频和音频的跳帧等机制进行了讨论,并提出了一种非锁相异步全数字视音同步实现方案。该方案采用了直接置数法恢复系统时钟,滞后跳帧法实现视频与系统时钟的同步,数字锁相法控制音频与系统时钟同步,最后,对视频帧率和音频PCM时钟的偏差等问题作了进一步的探讨。     

A wideband integrated circuit amplifier for fixed-gain application

Circuits which achieve precise gains without the use of negative feedback are of interest because of their simplicity and potential for achieving large bandwidths. A circuit architecture based upon precision current mirrors for producing fixed gains without the use of feedback has been reported in the literature and implemented on a BiCMOS process [1]. This paper provides further analysis of this approach and applies it to a new bipolar amplifier, intended for such applications as real-time active filter synthesis.     

电流型运算放大器在应用电路中的特性研究

文中简要介绍了电流型运放的特性,着重对电流型运放的应用电路进行测试,研究电流型运放的应用特性。实验中,选择典型电流型运放及电压型运放构建负阻变换器、电压跟随器和同相比例放大器,通过对此3类应用电路的测试,分析、总结运放参数对特殊应用电路的影响,为电路设计者在具体电路的设计中恰当选择适合的放大器提供参考。     

HDTV视频解码器中码率缓冲的实现方法

对于采用ＭＰＥＧ－２编码格式的视频流,由于视频信源的非平衡特性和不同类型帧采用不同的压缩算法,导致序列中各类型图像之间的数据量存在较大差异。而经解码后显示的帧速率是恒定的,这就要求在解码端有一个缓冲器来实现输入码率与输出码率间的过渡。基于此,介绍了ＭＰＥＧ－２标准中对码率缓冲器的有关规定,阐述了高清晰度电视视频解码器对码率缓存的实际要求,提出了一种实现码率缓冲器的方法。