1.2 Gbit/s fully integrated transimpedance optical receiver OEIC for 1.3-1.55 mu m transmission systems

The design and performance characteristics of a 1.2 Gbit/s transimpedance receiver OEIC incorporating a high voltage gain, low input capacitance cascode amplifier and a 50 Omega driver is reported. The receiver exhibited an improvement of factor of two in bandwidth over those using a conventional single inverter gain stage. An optical sensitivity of -27.5 dBm for an error rate of 10/sup -9/ at 1.3 mu m wavelength has been obtained without bandwidth equalisation or noise filtering.<>     

In0.53Ga0.47As junction field-effecttransistors as tunable feedback resistors for integrated receiverpreamplifiers

In_0.53Ga_0.47As active feedback junction field-effect transistors (JFETs) for use in integrated transimpedance photoreceivers are discussed. By varying the gate-to-source voltage V_GS, the resistance can be continuously tuned between 3 and 40 kΩ with a drain-to-source capacitance of <10 fF. The temperature coefficient of resistance is between -5 and -20 Ω/°C (for V_GS less than the pinch-off voltage). The combination of large resistance and low capacitance can result in high receiver sensitivity without sacrificing amplifier dynamic range. The feedback FET was fabricated adjacent to 1.8-μm-gate-length JFETs with transconductances of 110 mS/mm, gate-to-source capacitances of 1.3 pF/mm, and DC amplifier voltage gains of 100. The compatibility of these transistor structures indicates that an integrated preamplifier with dynamically tunable bandwidth can be realized     

Monolithic balanced p-i-n/HBT photoreceiver for coherent optical heterodyne communications

Two InGaAs p-i-n photodetectors connected in a balanced configuration have been monolithically integrated with a transimpedance preamplifier made from InP-InGaAs heterojunction bipolar transistors (HBTs) to realize a balanced optoelectronic integrated circuit (OEIC) receiver. The receiver, with a bandwidth of 3 GHz and a common mode rejection of 25 dB, has a sensitivity of -49 dBm at a bit error rate of 10/sup 9/ under NRZ FSK reception at 200 Mb/s.<>     

A 3 GHz transimpedance OEIC receiver for 1.3-1.55 μm fiber-opticsystems

A high-performance metal-semiconductor-metal high-electron-mobility transistor (MSM-HEMT) transimpedance photoreceiver fabricated using OMCVD-grown InAlAs/InGaAs heterostructures on an InP substrate is discussed. This is the first demonstration of a monolithically integrated receiver amplifier that incorporates a cascode amplifier stage and a Schottky diode level-shifting stage implemented on InP-based optoelectronic integrated circuit (OEIC) photoreceivers. The transimpedance amplifier has an open-loop gain of 5.7 and a bandwidth of 3.0 GHz, which represent the highest gain and the highest speed performance reported for 1.3-1.55-μm-wavelength OEIC receivers     

A proposed OEIC receiver using MESFET photodetector

An optical receiver configuration based on the concept of using a single optically gated metal-semiconductor-fieid-effect transistor (MESFET) to perform the function of a photodetector and preamplifier has been introduced. The proposed optoelectronic integrated circuit (OEIC) receiver has been analyzed theoretically. A simplified noise model of the receiver has also been developed. Results have been presented for an OEIC receiver based on InGaAs MESFET supposed to be fabricated with matured InGaAs-InP MMIC technology. Theoretical results based on a simplistic noise model reveal that the proposed OEIC receiver has superior performance characteristics over the existing optical receivers     

A 40 Gbit/s fully integrated optical receiver analog front-end in 90 nm CMOS

A fully integrated 40 Gbit/s optical receiver analog front-end (AFE) including a transimpedance amplifier (TIA) and a limiting amplifier (LA) for short distance communication is described in this paper.The proposed TIA employs a modified regulated cascode (RGC) configuration as input stage,and adopts a third order interleaving active feedback gain stage.The LA utilizes nested active feedback,negative capacitance,and inductor peaking technology to achieve high voltage gain and wide bandwidth.The tiny photo current received by the receiver AFE is amplified to a single-ended voltage swing of 200 mV(p p).Simulation results show that the receiver AFE provides conversion gain of up to 83 and bandwidth of 34.7 GHz,and the equivalent input noise current integrated from 1 MHz to 30 GHz is about 6.6 μA(rms).     

Sensitivity limits of long-wavelength monolithically integratedp-i-n JFET photoreceivers

Noise characteristics and factors which limit the sensitivity of long-wavelength monolithically integrated photoreceivers using InGaAs p-i-n photodiodes (PD) and InGaAs junction-held-effect transistors (JFET's) were analyzed with regard to the input-noise current and the open-loop gain. Effects of the JFET gate length and the parasitic capacitance on the sensitivity were also clarified. Three types of photoreceivers were fabricated by using metal organic vapor phase epitaxy (MOVPE)-grown crystals and Be-ion implantation technology. The receiver using a cascode input stage had an extremely high sensitivity (-35.4 dBm) for a 622-Mb/s NRZ, 13-μm-wavelength signal. The sensitivity of the other two receivers using an inverter input stage was moderate, -33.6 dBm for a multipower supply input stage and -31.4 dBm for a single power supply input stage     

Wide bandwidth low noise pinFET receiver for high-bit-rate opticalpreamplifier applications

A wide bandwidth low noise pinFET receiver has been fabricated and characterised for optical preamplifier applications. The receiver uses a low capacitance planar pin diode as the photodetector. A bandwidth of 7.08 GHz was measured. The measured input noise current for the receiver front-end is lower than 12 pA/√(f). Using a 1.3 μm DFB laser as the transmitter, at a data rate of 4 Gbit/s, the measured receiver sensitivity is -25.5 dBm with a bit-error-rate of 1×10 ^-9. A set of two of such receivers has also been tested in a 1.3 μm polarisation-insensitive optical preamplifier system experiment. The measured receiver sensitivity, including an optical insertion loss of 1.5 dB, is -29.3 dBm     

Multigigabit/s 1.5 μm λ/4-shifted DFB OEIC transmitterand its use in transmission experiments

Optoelectronic integrated circuit (OEIC) transmitters consisting of 1.5 μm λ/4-shifted distributed feedback (DFB) lasers and InGaAs-InAlAs MODFETs were fabricated for the first time. The entire processing requires only two organometallic vapor-phase epitaxy (OMVPE) growths, with the potential for high yield and low cost. Direct modulation of the OEIC transmitter is demonstrated for bit rates up to 10 Gb/s. A transmission experiment using the OEIC transmitter and a hybrid p-i-n/HEMT receiver is conducted at 5 Gb/s, with a sensitivity of -20 dBm and a bit-rate-distance product of 145 Gb/s-km     

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.     

A complete 400-Mb/s burst-mode data OEIC receiver

A fully integrated burst-mode GaAs MESFET optoelectronic integrated circuit (OEIC) receiver, 215 mil×109 mil, that has been designed and implemented for point-to-point data links for application as a phased-array antenna controller is described. The chip provides a low-cost means for passing 400-Mb/s antenna control information using fiber optics with a very low bit-error rate (BER). Approximately 350 source-coupled FET logic gates are present on the chip. A new data coding and timing recovery scheme that is highly tolerant to jitter over a wide bandwidth has been developed. The OEIC uses an on-chip metal-semiconductor-metal (MSM) photodiode with 0.12-A/W responsivity measured at 780 nm and was fabricated in a 1.0-mm GaAs MESFET manufacturing technology. The low capacitance semi-insulating GaAs substrate minimizes the coupling between analog and digital circuitry. The circuit operates from a single 5-V supply, consumes 1 W of power, and provides an 8-b CMOS output bus together with various utility flags. Optical sensitivity is estimated at -20 dBm for 10^-14 BER     

27-GHz bandwidth high-speed monolithic integrated optoelectronicphotoreceiver consisting of a waveguide fed photodiode and anInAlAs/InGaAs-HFET traveling wave amplifier

A monolithic integrated photoreceiver for 1.55-μm wavelength has been designed for operation in a 20-Gb/s synchronous digital hierarchy system (SDH/SONET), based on a new integration concept. The optoelectronic integrated circuit (OEIC) receiver combines a waveguide-integrated PIN-photodiode and a traveling wave amplifier in coplanar waveguide layout with four InAlAs/InGaAs/InP-HFETs (0.7-μm gate length). The receiver demonstrates a bandwidth of 27 GHz with a low frequency transimpedance of 40 dBΩ. This is, to our knowledge, the highest bandwidth ever reported for a monolithic integrated photoreceiver on InP. Furthermore, a receiver sensitivity of -12 dBm in the fiber (20 Gb/s, BER=10^-9) and an overall optical input dynamic range of 27 dB is achieved. Optical time domain multiplex (TDM) system experiments of the receiver packaged in a module show an excellently shaped eye pattern for 20 Gb/s and an overall sensitivity of -30.5 dBm (BER=10^-9) [including erbium doped fiber amplifiers (EDFA)]     

高灵敏度CMOS光电集成接收机设计

设计了一个由调节型级联跨阻抗放大器(TIA)和双光电二极管(DPD)构成的CMOS光电集成(OEIC)接收机.具体分析了这个光电集成接收机的噪声和灵敏度及其相互关系.接收机中的噪声主要是电路中电阻的热噪声和MOS器件的闪烁噪声.提出了优化接收机灵敏度的方法.通过低成本的CSMC 0.6μm CMOS工艺流片并对芯片进行了测试.从测试眼图可知,该CMOS光电集成接收机可工作在1.25GB/s的传输速率下,灵敏度为-12dBm.     

11 GHz bandwidth optical integrated receivers using GaAs MESFET andMSM technology

State-of-the-art performance of GaAs-FET-based monolithic optoelectronic integrated circuit (OEIC) receivers is reported. The OEIC receiver achieves -3-dB bandwidth as high as 11 GHz for optical signals at a wavelength of 850 nm. The feedback resistance of the receiver is 1000 Ω and the effective transimpedance into a 50 Ω load is 565 Ω. The effective transimpedance-bandwidth (TZBW) product is 6.1 THz-Ω. This ultra-high-performance receiver was implemented via a high-yield, low-cost direct ion implanted GaAs MESFET technology with a 0.6-μm gate length and a metal-semiconductor-metal (MSM) detector with 2-μm lines×3-μm spacings     

A 10 Gbit/s OEIC photoreceiver using InP/InGaAs heterojunction bipolar transistors

Metal organic molecular beam epitaxy (MOMBE) was successfully used for the first time to realise a high speed monolithic photoreceiver. Incorporating an InGaAs pin photodetector followed by a transimpedance preamplifier circuit implemented with InP/InGaAs heterojunction bipolar transistors (HBTs), the OEIC photoreceiver had a bandwidth of 6 GHz and a midband transimpedance of 350 Omega . In a system experiment performed at 10 Gbit/s, the receiver exhibited a sensitivity of -15.5 dBm for a bit error rate of 10/sup -9/ at a wavelength of 1.53 mu m. This is the first demonstration of operation of a long wavelength OEIC photoreceiver at this speed.<>     

Narrow-gate In0.53Ga0.47As junctionfield-effect transistors as tunable resistors for long-wavelengthintegrated optical receivers

The fabrication of In_0.53Ga_0.47As junction field-effect transistors (JFETs) for use as active feedback resistors in integrated transimpedance photoreceivers is described. Transistors using both air-bridge and non-air-bridge technologies are described. Varying the gate-to-source voltage (V_GS) allows the output resistance to be tuned continuously between 3 and 40 kΩ with a drain-to-source shunt capacitance of less than 10 fF. The temperature coefficient of the output resistance is between -5 and -20 Ω/°C (for V_GS less than the pinch-off voltage). The combination of large resistance and low shunt capacitance can result in high receiver sensitivity without sacrificing amplifier dynamic range. The feedback FETs are fabricated adjacent to 1.8-μm gate JFETs with transconductances of 110 mS/mm and gate-to-source capacitances of 1.3 pF/mm     

A 156-Mb/s CMOS optical receiver for burst-mode transmission

In a point-to-multipoint fiber-optic subscriber system using TDMA (time division multiple access), the receiver should be able to handle burst-data packets with different amplitudes, Moreover, high-bit-rate operation is desired for multimedia communications. The operational speed is mainly restricted by the input parasitic capacitance of the preamplifier. Reducing the input impedance of the preamplifier widens its frequency bandwidth, and it makes high-speed operation possible. A multistaged preamplifier using feedforward phase compensation technique has been devised for small input impedance with stable operation at high frequency. Multistaged feedforward bias control is used for quick response to burst data, and the time constant is also reduced for high-speed operation. Using these design techniques, an optical receiver IC was fabricated using standard 0.5-μm CMOS technology. The instantaneous response receiver has high sensitivity of -35.6 dBm, a wide dynamic range of more than 26 dB for burst-mode optical input at 156 Mb/s, and requires no external adjustment. The use of standard CMOS technology and the freedom from external adjustment make it possible to build an inexpensive receiver module     

1Gb/s CMOS调节型共源共栅光接收机

基于特许0.35μm EEPROM CMOS标准工艺设计了一种单片集成光接收机芯片,集成了双光电探测器(DPD)、调节型共源共栅(RGC)跨阻前置放大器(TIA)、三级限幅放大器(LA,limiting amplifier)和输出电路,其中RGCTIA能够隔离光电二极管的电容影响,并可以有效地扩展光接收机的带宽。测试结果表明,光接收机的3dB带宽为821MHz,在误码率为10-9、灵敏度为-11dBm的条件下,光接收机的数据传输速率达到了1Gb/s;在3.3V电压下工作,芯片的功耗为54mW。     

光收发器中光电集成接收芯片的实现

针对应用于850nm光通信中的10/100Mbit/s收发器,提出采用0.5μm标准CMOS工艺对其光接收芯片实现Si基单片集成。整体芯片面积为0.6mm2,共集成了一个双光电二极管的(DPD)光电探测器和一个跨阻前置放大电路,功耗为100mW,并给出了具体的测试性能结果。结果表明,在850nm光照下,光接收芯片带宽达到53MHz,工作速率为72Mbit/s。重点介绍了DPD光电探测器的原理和结构,并给出了相应的制造过程和电路等效模型,对整个光接收芯片进行了多种实用性测试,可以满足系统的性能要求。     

Optical preamplifier using optical modulation of amplified spontaneous emission in saturated semiconductor optical amplifier

This paper demonstrates a novel optical preamplifier using optical modulation of amplified spontaneous emission (ASE) emitted from a saturated semiconductor optical amplifier (SOA). Requirements on optical alignments and antireflection coating for SOAs can be relaxed and the elimination of an optical filter gives us a large tolerance of an input light wavelength in the proposed optical preamplifier. A small-signal gain of a fabricated preamplifier was over 13.5 dB for an input power of below -20 dBm. An optical gain bandwidth was over 60 nm. We measured the small-signal response of the optically modulated ASE. The 3 dB bandwidths at SOA bias currents of 200, 300, and 400 mA were 5.8, 12.6, and 16.5 GHz, respectively. We also investigated improvements in receiver sensitivities with the proposed optical preamplifier. Our calculation shows a possibility of 10 dB improvement in receiver sensitivities by using the optical preamplifier at 10 Gb/s. The measured receiver sensitivity was -22.7 dBm at 10 Gb/s with the optical preamplifier, which is corresponding to an improvement of 2.5 dB in the receiver sensitivity. Further improvements of the receiver sensitivity can be expected by optimizing the structure of SOAs for saturating ASE.