一种电子系统认证芯片的电源规划

为了对所开发的电子产品进行保护,采用ASIC的方法设计基于硬加密技术的电子系统认证芯片。在后端物理设计中,为了使最终的芯片实现面积优化且满足功耗、时序等要求,采用预设计的方法对芯片进行功耗预估与布线拥塞分析。根据分析结果提高了芯片利用率,并针对预设计中存在的电压降（IR Drop）违规进行了详细的电源规划．包括全局电源网络的连接、电源环和电源条的设计．最终满足了功耗要求,实现了时序收敛以及面积优化。     

New defect size distribution function for estimation of chip critical area in integrated circuit yield models (CMOS)

The Gamma function is proposed to approximate the measured lithographic defect size distribution for the estimation of the chip critical area. It is shown that, compared to the commonly used 1/x/sup 3/ function for approximation of the lithographic defect size distribution, the Gamma function provides much better agreement with the measured data, thus leading to a more accurate estimation of the chip critical area.<>     

A frequency offset estimation algorithm for OFDM systems

A new fine carrier frequency offset estimation algorithm in Orthogonal Frequency Division Multiplexing （OFDM） system is proposed. The correlation item is the training sequence instead of the received signal in the new algorithm. Simulation results show that the performance of the new algorithm is 4dB-9dB better than that of Schmidl＇s algorithm. Coarse frequency offset estimation is also discussed in this paper, which is the improvement of Zhang＇s method. The estimation range using the improvement method is twice as that using the Zhang＇s method. Based on the hardware of the receiver and the improved algorithm, a method using Fast Fourier Transform （FFT） is proposed to implement the coarse frequency estimation. The chip area of OFDM system can be reduced by using the proposed method.     

Novel FDTD simulation method using multiple-analysis-space for electromagnetic far field

Wide-band undesired electromagnetic noise near electronic systems, which includes small noise source like the printed circuit board (PCB), is a current problem in the field of electromagnetic interference. However, the estimation method for the electromagnetic noise near a system under test has not been established. This paper proposes a newly developed estimation method of the electromagnetic noise for a wide area, from near to far field, using the finite difference time-domain (FDTD) method. The proposed FDTD simulation method is an estimation technique for near to far field with multiple analysis spaces (MAS). The MAS has an internal analysis space (IAS) and an external analysis space (EAS). The analysis near a radiation source can be calculated in the IAS. The EAS is the outside space from IAS, which is for calculation of the far field. It is expected that the proposed FDTD method by MAS (FDTD-MAS) decrease in the calculation cost in terms of computational time and memory costs, especially for estimation of radiation from PCB. The principle procedure of the FDTD-MAS method is described in the first part of this paper. As example of advantages of the calculation and confirmation of the calculation accuracy, the electric field distributions radiated from a 1-GHz half-wavelength dipole antenna in an IAS of 0.3/spl times/0.3 m/sup 2/ area and an EAS of 7/spl times/7 m/sup 2/ area are used as examples. When the cell size ratio of IAS to EAS is changed from 6 to 20, the FDTD and theoretical values show good agreement. It is indicated that the FDTD-MAS simulation method is one of the most powerful tools for the estimation of electromagnetic noise from near field to far field from small and thin source.     

图像采集综合评估的嵌入式指纹识别系统

为提高指纹采集与指纹图像数据处理的效率,设计一种新型的指纹识别系统,采用了专用指纹芯片、指纹传感器芯片和LCD显示模块。设计了一种指纹图像综合评估算法,采用综合基于方向图的灰度值计算、计算灰度值的前背景分割、计算优势方向块的图像质量分析、计算灰度均值和标准差的指纹图像干湿程度分析、指纹位置的分析等技术和方法,对指纹图像进行处理,并将指纹图像的评估结果输出到显示屏上。系统已应用于医疗机构的EMR系统中。     

基于二次4阶矩切片的DS-CDMA信号盲检测

直接序列码分多址(DS-CDMA)在现代民用和军用通信系统得到了广泛应用,DS-CDMA信号盲检测已引起研究者的关注.利用4阶矩切片m4x(0,0,τ)能很好地抑制高斯噪声的特点,在改善4阶矩切片估计的基础上,提出一种二次4阶矩切片检测方法,解决了4阶统计量估计误差和计算量大的问题.仿真结果表明,该方法性能优于平方倍频法、二次谱法和倒谱法等,在虚警概率为1%,信噪比为-22 dB时,检测概率可达90%.     

CMOS图像传感器芯片的自动白平衡算法

针对CMOS图像传感器芯片中的自动白平衡图像处理电路,提出了一种便于硬件实现的增益计算方法,并在此基础上实现了一个用于CMOS图像传感器芯片的自动白平衡算法。该算法将增益计算的计算法与迭代法结合使用,并用比较器和移位寄存器来取代复杂的组合逻辑单元,在不增加硬件开销的基础上提高了计算精度与处理速度。     

Visual telephony as an ISDN application

The key factors deterring the use of visual telephony are identified, and an overview of a typical system architecture is given. The video signal formats and video and audio coding algorithms used are described. Video codec implementation is considered, and an implementation based on application-specific integrated circuits is presented. In particular, three key signal processing modules in the video codec are examined: a discrete cosine transform chip, a motion estimation chip, and a variable-length codec chip. Standardization activities in the video coding area are discussed     

Accurate estimation of defect-related yield loss in reconfigurableVLSI circuits

A general methodology for accurate estimation of defect-related yield loss in reconfigurable VLSI circuits is presented. Yield for replicated cells in the reconfigurable circuitry is estimated based upon a calculation of layout sensitivity to manufacturing defects of varying sizes. The important concept addressed is the need for separate estimation of reconfigurable and nonreconfigurable components of a replicated cell's critical area (CA) for accurate yield estimation. Two examples-a 256 kb SRAM and reconfigurable 32×32 port 32 b crossbar switch-are presented to illustrate the essential characteristics of the proposed yield estimation method     

SMT电路板组件的动态特性分析

设计制作了一块由不同封装形式和材料参数的芯片集成的SMT电路板组件。根据各芯片和PCB板的参数建立了有限元模型,通过有限元仿真对该组件进行了不同约束条件下的模态分析及瞬态冲击动态响应分析,得到了该组件的前五阶固有频率(四角约束条件下分别为862.07,1144.70,1445.20,1915.50和1941.70Hz)及相应频率下的模态参数。并通过实验和仿真结果的对比验证了所建立的有限元模型基本正确,该模型可作为组件疲劳寿命估计和结构优化的基础。提出了芯片布局优化及提高可靠性的建议。     

Maximization of Good Chips Per Wafer by Optimization of Memory Redundancy

In the optimization of the number of good chips per wafer, yield is obviously one key factor. It plays the major role in the manufacturing phase, as at this time circuit design and chip area cannot be modified. In the design phase, however, chip area as the second factor defining good chips per wafer can still be influenced. If there are no strong relationships between yield and chip area, both can be optimized independently. In some cases, however, there are such strong relationships, and an optimum of yield gain versus area growth has to be found. Maybe the most important example where strong relationships between area and yield have to be considered is the estimation of optimum memory redundancy. In this paper, we will review and discuss relationships between yield and area and present methods for optimization of good chips per wafer, with special focus on the optimization of memory redundancy     

An advanced area scaling approach for semiconductor burn-in

In semiconductor manufacturing, early life failures are avoided by putting the produced items under accelerated stress conditions before delivery. The products’ early life failure probability p is assessed by means of a burn-in study, in which a sample of the stressed items is investigated for early failures. The aim is to prove a target failure probability of the produced devices and release stress testing of the whole population. Given the failure probability level on a reference product, the failure probabilities of so-called follower products with different chip sizes are then obtained by means of area scaling. Classically, area scaling is done with respect to the whole area of the chips. Nevertheless, semiconductors can be partitioned into different chip subsets, which can have different likelihoods of failures. In this paper, we propose a novel area scaling model for the chip failure probability p, which enables us to scale the chip subsets separately from each other. The main idea is to adapt the classical estimators of the failure probabilities of the chip partitions according to the number of failures on the different chip subsets. This leads to a more appropriate estimation of the failure probabilities of the follower products and helps to improve the efficiency of burn-in testing.     

An interactive VLSI CAD tool for yield estimation

The yield of a VLSI chip depends on the sensitivity of the chip to defects occurring during the fabrication process, among other factors. To predict this sensitivity, one usually needs to compute the so-called critical area (A_c), which reflects how many and how large the defects must be in order to result in a circuit failure. The main computational problem in yield estimation is to calculate A_c efficiently for complicated, irregular layouts. A novel approach is suggested for this problem that results in an algorithm that will solve it efficiently. This paper provides an interactive, accurate, and fast method for the evaluation of critical area as a design tool; the tool utilizes good visual feedback to allow layout improvement for higher yield. The algorithm is compared to other yield-prediction methods, which use either the Monte Carlo approach (VLASIC) or a deterministic approach (SCA); the algorithm is shown to be faster. It also has the advantage that it can graphically show a detailed `defect sensitivity map' that can assist a chip designer in improving the yield of his/her layout     

基于热-流-力耦合计算的多芯片组件布局构形优化

基于构形理论和多物理场耦合数值计算方法,建立了自然对流条件下均匀产热的多芯片组件模型,给定印刷电路板面积和芯片总占地面积为约束条件,分别以最高温度、最大应力和最大形变为优化目标,以芯片个数及芯片长宽比为设计变量,研究了芯片布局演化对系统性能的影响.结果 表明:不同优化目标下,最优构形均为芯片长宽比为2.1的8芯片布局方式,多芯片组件的最高温度、最大应力和最大形变分别最多可降低16.5％,28.3％和26.9％.对芯片个数和芯片长宽比双自由度的优化效果要明显优于仅对芯片长宽比的单自由度优化.     

CDMA信号码片内多径时延估计算法

针对CDMA信号的特点,提出了低信噪比条件下估计延迟差小于一个码片周期的多径信号时延的有效算法,该文首先建立了一个能够有效抑制噪声影响的多径功率延迟函数,然后推导了建立在此函数基础上的高分辨率时延估计算法,给出了算法的具体步骤,分析了算法的性能,最后通过对比仿真和性能仿真证明了该方法具有低信噪比条件下高频谱分辨率的特点。     

Improved method for determining the shear strength of chip component solder joints

In this paper an improved method has been presented to determine the solder joint shear strength of passive discrete surface mounted (SMD) chip components (like resistors and capacitors).To calculate the stress in a solder joint in the case of shear loading, the force applied should be measured and the amount of joined surface (wetted area of the component metallization) calculated.Using the method we suggest, we first measured the exact position of the chip component after soldering according to the guidelines set out in standard IPC 9850 (Institute for Interconnecting and Packaging Electronic Circuits). To determine the accurate value of the joined surface, a 3D profile calculation was carried out taking into account the exact position of chip components after soldering. The calculation of the profile was based on the principle of minimum energy. Then, the next stage was to determine the maximum force experimentally that the solder joint was able to withstand before failure in shear. The evaluation of the shear load results verified that the standard deviation coefficient of the results was lower when the shear strength of the solder is characterized by the maximum stress instead of maximum force. It was proved by our experiments and by simulations that the shear strength of misaligned components solder joints depends on the degree of component misalignment after reflow soldering.     

A real-time motion estimation and compensation LSI with wide searchrange for MPEG2 video encoding

This paper presents a motion estimation and compensation large scale integration (LSI) for the MPEG2 standard. An embedded RISC processor and special hardware modules enable the LSI to achieve a sufficient ability to perform real-time operation and provide the availability to realize many kinds of block matching algorithms. Using a three-step hierarchical telescopic search algorithm, a single chip accomplishes real-time motion estimation with search ranges of ±32.5×±32.5 pixels for motion vectors. The chip was fabricated using 0.5-μm CMOS technology and has an area of 16.5×16.5 mm² and 2.0 M transistors     

基于多层板弯曲理论的芯片翘曲变形分析

将芯片简化为层合板,基于弹性力学的多层板弯曲理论,通过求解板弯曲微分方程,得到芯片在自由边界约束条件下的温度翘曲变形的解析表达式。该芯片翘曲变形表达式可以反映材料参数随温度的变化,为再流焊温度变化幅度较大的芯片翘曲分析提供了有效的快速计算方法。通过与有限元分析计算结果及实测结果的对比,表明理论计算结果基本符合实际情况,层合板简化模型近似程度可以满足工程预估分析的要求。     

基于多分辨分析的集成元件管脚微位移检测

由于电子集成元件的管脚朝着多且细的方向发展,管脚偏移检测要求提高,一般的检测方法不能满足这样高的精度。本文研究了采用光电自动快速检测大尺寸、多管脚集成块管脚位置微偏移的方法,提出了基于多分辨分析（MRA）的微位移的检测技术,达到亚像素的检测精度,具有良好的可靠性,解决了大型集成块管脚位置偏差自动化检测问题。     

相位编码信号的谱相关分析与调制参数估计

对BPSK和QPSK信号的谱相关性进行了详细的理论分析,并通过计算机仿真得到了两种信号的谱相关图,最后利用信号谱相关函数特征谱的非零循环频率处峰值的位置估计出信号的载频和码元速率,并通过仿真实验对估计算法性能进行了评估,该方法在低信噪比的情况下也具有较好的估计效果。