Low switching noise and load-adaptive output buffer designtechniques

Switching noise due to di/dt is becoming severe as technology states, resulting in a great need for noise-suppression techniques. Several techniques to reduce the switching noise caused by output buffers in CMOS chips are described. An ac/dc output buffer design technique is proposed that includes an innovative feedback mechanism to reduce switching noise and output signal ringing while at the same time maintains timing and dc current requirement. Also, a technique of adaptively separated simultaneous switching noise is proposed that can increase the number of simultaneously switching outputs per V_DD and GND pair. Measurement results show that the ac/dc buffer can reduce the output ringing by 2.5× and VDD/GND line bounce by 1.7× and the ASN can double the number of simultaneous switching outputs under the same conditions as compared to the weighted and distributed buffer     

一种抗负压和抗共模噪声的全集成GaN电平位移电路

设计了一种基于全集成GaN工艺平台,具有抗负压、抗共模噪声的电平位移电路。相较于传统的电平位移电路,通过电路设计将驱动部分的低电压域同高侧部分电路的低电压域保持一致,实现了抗负压的功能。除此之外,针对半桥驱动开关节点的抬升、下降引起内部电容充放电并导致信号逻辑错误的问题,对高侧部分电路进行设计,实现了抗共模噪声的能力。在200 V GaN工艺下,电平位移电路将0～6 V的输入信号转换至200～206 V。仿真结果表明,该电平位移电路的上升传输延时为4.74 ns,下降传输延时为4.11 ns,抗开关节点负压为-4 V,具有100 V/ns共模噪声抑制能力。     

High temperature performance of NMOS integrated inverters and ringoscillators in 6H-SiC

Electrical characterization up to 573 K is performed on integrated inverters with different beta ratios and 17-stage ring oscillators based on SiC NMOS technology. These devices are fabricated on a p-type 6H-SiC epitaxial layer with a doping concentration of N_A=1·10 ¹⁶ cm^-3. The n⁺ source/drain regions and buried channels for depletion-mode load transistors are achieved by ion implantation of nitrogen. Direct current measurements of the inverters with a 5 V power supply yield proper output levels and acceptable noise margins both at 303 and 573 K. Dynamic measurements with square waves show the full voltage swing up to 5 kHz in this temperature range. The 17-stage ring oscillators, driven by a 5.5 V power supply, show an oscillator frequency of 625 kHz at 303 K, which corresponds to a 47 ns delay per inverter stage. This time constant increases only to 59 ns at 573 K. The temperature drift of the measured output signal is well below 30% up to this elevated temperatures. During 20 heat cycles up to 573 K in air, no measurable drift in circuit parameters occurred. In addition, only a slight dependence of the oscillator frequency on supply voltage is observed     

分段式电流舵 D/A转换器抗di/dt噪声设计

设计了一个8位50MHzD/A转换器(DAC),采用5+3分段式电流舵差分输出结构,其中高5位采用温度计码方式译码,低3位采用二进制译码方式;从各电路模块设计结构上提高DAC抗di/dt噪声的能力;设计了一个低交叉点开关驱动电路,有效地降低了输出毛刺,减小了数字电路di/dt噪声的影响。采用VIS0.35μmCMOS工艺进行仿真,结果表明,微分非线性(DNL)和积分非线性(INL)均小于0.15LSB。     

An EBS (electron bombarded semiconductor) high-current pulse amplifier

An EBS (electron bombarded semiconductor) pulse amplifier which generates high-current fast-risetime variable-width pulses into low impedance loads is described. Current pulses of 100 A into a 1-Ω load have been obtained with a risetime of 2.2 ns. A di/dt of 40 000 A/µs and a dV/dt of 71 000 V/µs have been obtained. Pulse lengths to 1 µs at 0.1-percent duty have been achieved. The risetime and peak current capabilities are presently limited by internal circuit parasitics. Without parasistics, the theoretical peak output capabilities for this EBS are 340 A with a di/dt of 6 × 10⁵A/µs.     

Differential bidirectional transceiver for on-chip long wires

This work presents a differential bidirectional transceiver (DBT) for on-chip long wires. To enhance operating speed and reduce power consumption, the voltage swing on the wire is reduced using current-mode scheme. Consequently, our design performs higher data rate when wire length is extended. Moreover, adoption of differential scheme with a moderate tradeoff of area effectively lowers power supply noise and common mode noise. The receiver adopts four input differential pairs along with current summation circuit to evaluate small signal differences of every that state resulted from transmitting different data. Simulations using 0.18-μm device model indicates that the total input to output delay over a 5 mm long wire is 0.96 ns, with a power consumption of 8.724 mW at a speed of 1.2 Gbps and a maximum achievable data rate of 1.5 Gbps. A test chip is realized and successfully verifies the performance of the transceiver.     

New full-voltage-swing BiCMOS buffers

Circuit techniques are presented for increasing the voltage swing of BiCMOS buffers through active charging and discharging using complementary bipolar drivers. These BiCMOS circuits offer near rail-to-rail output voltage swing, higher noise margins, and higher speed of operation at scaled-down power supply voltages. The circuits are simulated and compared to BiCMOS and CMOS buffers. The comparison shows that the conventional BiCMOS and the complementary BiCMOS buffers are efficient for power supply voltages greater than 3V and that if the power supply voltage is scaled down (<3 V) and the load capacitance is large (>1 pF), the complementary BiCMOS buffers would be the most suitable choice. They provide high speed and low delay to load sensitivity and high noise margins. The first implementation is favorable near a 2.5-V power supply for its smaller area     

dv/dt Noise canceling circuit in ultra-high-voltage MOS gate drivers

A novel small-sized voltage mode noise canceling circuit is introduced in order to remove the dv/dt noise in the ultra-high-voltage MOS gate drive IC more efficiently, accurately and steadily. The dv/dt noise is removed completely by the mutual controlling of the high-side voltage signal, which improves the incapability of the full removal of dv/dt noise by conventional noise remove circuit due to the mismatch in the high-side circuit. In addition, no additional circuit is introduced to the noise canceling circuit. Fabricated in 700 V 0.5 μm BCD with simulation tool HspiceD, the circuit shows good performances of a quiescent current less than 50 μA, and a full removal of 70 V/ns dv/dt noise by the noise elimination function block. Moreover, a mismatch rate ranging within ±100 % can also be fully eliminated, thus ensuring the stability and reliability of the ultra-high-voltage gate driver’s performance.     

A Novel Method of Active Power Noise Cancellation in I/O Buffers

This paper presents a scheme to reduce the on-die voltage noise that occurs due a buffer switching event. Both output and input buffer switch events are addressed. A generic power delivery network (PDN) model with parasitic inductance is assumed. A change in current ( ${rm di}/{rm dt}$) across the inductor is considered the primary cause of the voltage noise. On-die decoupling capacitance is traditionally added to the power delivery network to address this problem and to limit the droop. The method described in the paper shows a principally different approach. The maximum ${rm di}/{rm dt}$ is managed to reduce the voltage noise. It is proposed to send to a buffer a current waveform from an external supply or to recycle charge from a locally charged capacitance when the ${rm di}/{rm dt}$ occurs, thus substantially reducing the on-die voltage noise. Alternatively, at a given acceptable level of voltage noise the on-die capacitance can be reduced, providing significantly lower product cost. This paper provides theoretical and modeling background of the proposed schemes and includes simulation results on several performance characteristics.      

Low-power CMOS/BiCMOS drivers and receivers for on-chipinterconnects

Novel low-voltage swing CMOS and BiCMOS driver/receiver circuits for low-power VLSI applications are proposed. Interconnect wire drivers with low output signal swing are employed. Special receivers provide single and double level conversion while minimizing the total driver/receiver transmission delay. These level converters have no DC power dissipation. At 3.3 V power supply voltage, the proposed circuits consume less power without delay penalty. The power saving is observed to be as high as 30%. At lower supplies further power and delay improvements are observed     

基于门控多周期积分的背景抑制读出电路

在空间遥感领域,波长在3μm～5μm的中红外焦平面探测器大都工作在高背景环境下,信号电流远小于背景电流.为解决当前信号淹没于背景这一突出问题,设计了一种采用门控多周期积分结构实现的背景抑制功能的读出电路.该电路在抑制背景电流(包括暗电流)的同时能有效降低噪声,提高有效积分时间,增大输出信号动态范围.经Spectre仿真软件验证了电路设计的正确性.背景电流输入范围为0 nA～110 nA,能够有效读出2.5 nA～25 nA之间的信号电流,电路输出摆幅大于2V.该电路的设计不仅能解决当前工程中的关键问题,还对今后高性能大面阵红外焦平面高背景弱信号探测具有重要的指导意义.     

High Speed and Low Energy Capacitively Driven On-Chip Wires

We present circuits for driving long on-chip wires through a series capacitor. The capacitor improves delay through signal pre-emphasis, offers a reduced voltage swing on the wire for low energy without a second power supply, and reduces the driven load, allowing for smaller drivers. Sidewall wire parasitics used as the series capacitor improve process tracking, and twisted and interleaved differential wires reduce both coupled noise as well as Miller-doubled cross-capacitance. Multiple drivers sharing a target wire allow simple FIR filters for driver-side pre-equalization. Receivers require DC bias circuits or DC-balanced data. A testchip in a 180 nm, 1.8 V process compared capacitively-coupled long wires with optimally-repeated full-swing wires. At a 200 mV swing, we measured energy savings of 3.8x over full-swing wires. At a 50 mV swing, we measured energy savings of 10.5x. Throughput on a 14 mm wire experiment due to capacitor pre-emphasis improved 1.7x using a 200 mV swing.     

Minimizing Phase Noise Variation in CMOS Ring Oscillators

The variation of phase noise across the frequency of operation of a CMOS ring oscillator is described analytically. The delay element of the ring oscillator considered comprises of a source-coupled differential pair with an active load element. In this circuit topology where the frequency of oscillation is varied by changing the resistance of the load, theory derived in this work predicts that phase noise will remain constant if constant output swing is maintained. Such an oscillator is designed in a 0.5 m CMOS process and the simulation results verify the theoretical analysis. Consequently, an oscillator design methodology is provided that dramatically reduces the phase noise optimization problem to just one frequency within the oscillator's output frequency range.     

A low-inductance line-frequency commutated rectifier complying with EN 61000-3-2 standards

This paper presents a high power factor rectifier, based on a modified conventional rectifier with passive L-C filter, which utilizes a line-frequency-commutated switch and a small auxiliary circuit in order to improve both harmonic content of the input current and power factor, thus allowing compliance with EN 61000-3-2 European standards. Being the switch turned on and off only twice per line period, the associated losses are very small. Moreover the limited di/dt and dv/dt considerably reduce the high-frequency noise emission, thus avoiding heavy EMI filters. The switch operation results in a boost action, which compensates for the filter inductor voltage drop, thus providing output voltage stabilization against load variations. Compared with other similar approaches, the presented topology can achieve higher power levels with a reasonable overall magnetic component size.     

I/SUP 2/L with polysilicon diode contact

A polysilicon diode is used instead of a Schottky diode in I/SUP 2/L/MTL to reduce the signal swing. The new method enables improvement of the power-delay product of a conventional I/SUP 2/L, which has heavily doped collectors, without detriment to process simplicity, while retaining high-packing density and compatibility with other bipolar circuits. Experiments demonstrate a factor of 2.5 to 3 improvement in propagation delay at a low-current level. However, high-current operation is restricted by decreased noise margin with increasing current level.     

Low-Power BiCMOS Optical Receiver With Voltage-Controlled Transimpedance

An optical receiver with voltage-controlled transimpedance using a current conveyor and a voltage amplifier monolithically integrated with a PIN photodiode in 0.6 mum BiCMOS technology is presented. The transimpedance is directly proportional to a voltage-controlled resistance, and can be continuously varied by changing its control voltage. Thanks to the mixed current-mode and voltage-mode signal processing, the bandwidth of the optical receiver is virtually independent of the photodiode capacitance. A linearity error smaller than 3.1%, a sensitivity dynamic range of 78.8 (37.9 dB) with the largest sensitivity of S = 890 mV/muW at 660 nm, an offset voltage smaller than 0.53 mV, a largest maximum power consumption of only 3.2 mW, a small-signal frequency bandwidth up to 189 MHz, a large-signal rise time/fall time down to 3.7 ns/3.3 ns, and an output noise level down to -77.8 dBm (for a frequency of 50 MHz and a resolution bandwidth of 30 kHz) are achieved     

Power Converter EMI Analysis Including IGBT Nonlinear Switching Transient Model

It is well known that very high dv/dt and di/dt during the switching instant is the major high-frequency electromagnetic interference (EMI) source. This paper proposes an improved and simplified EMI-modeling method considering the insulated gate bipolar transistor switching-behavior model. The device turn-on and turn-off dynamics are investigated by dividing the nonlinear transition by several stages. The real device switching voltage and current are approximated by piecewise linear lines and expressed using multiple dv/dt and di/dt superposition. The derived EMI spectra suggest that the high-frequency noise is modeled with an acceptable accuracy. The proposed methodology is verified by experimental results using a dc-dc buck converter     

Fibre-optic recirculating analogue delay line

A 0.5 ms delay line with a time-bandwidth product of > 105 is demonstrated by recirculating a 2 ns pulse around a 20.4 km single-mode fibre five times. Analogue signal regeneration is employed after each recirculation. System dynamic range, signal/noise ratio and cancellation ratio for a noncoherent moving target indicator radar application are given.     

基于过采样的DS-SS/BPSK信号延迟相乘多重相关检测

提出一种基于过采样的直接序列扩谱（Direct—Sequence Spread Spectrum，DS—SS）/二进制相移键控（Binary Phase Shift Keyed，BPSK）信号延迟相乘多重相关检测方法，并推导了延迟相乘相关原理，分析了基于过采样的延迟相乘相关方法对输出信噪比（Signal to Noise Ratio，SNR）的影响。理论推导和仿真证明，基于过采样的延迟相乘恢复DS—SS／BPSK信号载波方法保留了待测信号中噪声的高斯白噪声特性；采用多重相关的方法还可进一步提高输出信噪比。     

一种低功耗CMOS可编程模拟延时电路

提出了一种基于65 nm CMOS工艺的5位可编程模拟延时电路。采用1.2 V的电源电压和0.01 V的步进控制电压来实现方波输入信号的延时控制。利用Cadence软件对该延时电路进行了性能分析。仿真结果表明,在典型低阈值工艺角下,该延时电路利用5位延时控制信号达到了0.34 ns/LSB的最高延时分辨率和41.47 ns的最长输出延时,实现了对1 kHz~1 MHz范围的数字方波信号的有效延时控制。该延时电路适用于低频数据采集、数据存储等系统。