大规模集成电路抗热载流子设计

文章主要介绍了热载流子效应机理及产生原因，从其机理出发着重介绍了抗热载流子效应的设计方法。影响CMOS电路热载流子效应的因素有：晶体管的几何尺寸、开关频率、负载电容、输入速率以及晶体管在电路中的位置。通过对这些因素的研究，文章提出了CMOS电路热载流子可靠性设计的通用准则。     

深亚微米MOS器件的热载流子效应

对深亚微米器件中热载流子效应(HCE)进行了研究.还研究了沟道热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种典型的偏置条件的关系.在分析热载流子失效机理的基础上,讨论了热载流子效应对电路性能的影响.提出影响晶体管热载流子效应的因素有:晶体管的几何尺寸、开关频率、负载电容、输入速率及晶体管在电路中的位置.通过对这些失效因素的研究并通过一定的再设计手段,可以减少热载流子效应导致的器件退化.     

深亚微米MOS器件的热载流子效应

对深亚微米器件中热载流子效应(HCE)进行了研究.还研究了沟道热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种典型的偏置条件的关系.在分析热载流子失效机理的基础上,讨论了热载流子效应对电路性能的影响.提出影响晶体管热载流子效应的因素有:晶体管的几何尺寸、开关频率、负载电容、输入速率及晶体管在电路中的位置.通过对这些失效因素的研究并通过一定的再设计手段,可以减少热载流子效应导致的器件退化.     

深亚微米MOS器件的热载流子效应

对深亚微米器件中热载流子效应 (HCE)进行了研究 .还研究了沟道热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种典型的偏置条件的关系 .在分析热载流子失效机理的基础上 ,讨论了热载流子效应对电路性能的影响 .提出影响晶体管热载流子效应的因素有 :晶体管的几何尺寸、开关频率、负载电容、输入速率及晶体管在电路中的位置 .通过对这些失效因素的研究并通过一定的再设计手段 ,可以减少热载流子效应导致的器件退化 .     

一种基于0.5μm CMOS工艺圆片级可靠性评估方法

论文提出了0.5μm CMOS工艺圆片级可靠性(WLR)评估的方法,为工艺、电路可靠性提高和及时在线控制开拓了新思路。论文针对0.5μm工艺中金属电迁移以及器件热载流子等失效项,分别给出了相关内容的工艺物理机理、测试结构、测试方法和结果。测试得出单一电迁移失效、热载流子失效寿命可以达到1×109数量级(几十年),初步实现了工艺可靠性的在线监控。     

动态应力下MOSFET的热载流子效应与可靠性

叙述了动态应力下MOS器件和电路的热载流子效应及可靠性研究进展。对当前MOS电路中的动态应力热载流子退化现象及其物理机制进行了详细论述,为动态应力下CMOS电路热载流子可靠性研究奠定了基础。还对动态应力热载流子可靠性的准静态表征方法进行了讨论。     

微电子工艺技术可靠性

对工艺过程进行评估的目的在于找出存在可靠性缺陷的地方，它是针对技术磨损的机理，通过对专门设计的测试结构进行封装级或圆片级可靠性测试，获取可靠性模型参数和可靠性信息，超大规模集成电路主要的三个的失效机理分别是热载流子注入效应，金属化电迁移效应和氧化层的TDDB击穿，本文对这三种失效机理分别进行了介绍，对各自对应的可靠性模型进行了说明，列举了热载流子汪入效应的寿命评价实例，说明了可靠性评价的重要性，给出了可靠性主人在工艺中的应用流程图。     

CMOS数字电路抗热载流子研究

介绍了热载流子效应与电路拓扑结构及器件参数之间的关系,并在此基础上提出了基本逻辑门的一些搞热载流子加固方法。通过可靠性模拟软件验证这些方法,为CMOS数字电路提高抗热载流子能力提供了参考。     

GaAs IC能否达到硅VLSI的可靠性

硅VLSI技术和可靠性硅VLSI技术在过去的20年中有了很大的进步。VLSI的尺寸越来越小,而功能和复杂程度又越来越高。即使为了保持VLSI芯片可靠性的原有水平都必须提高元器件和互连的可靠性.例如,在1990年4Mbit的存储器上每个晶体管的可靠性至少必须相当于1970年4Kbit存储器的1000倍。而对互连的可靠性要求则更高.目前的硅VLSI技术是以CMOS FET(CMOS场效应晶体管)技术为基础的。现代先进的硅VLSI技术有四层互连。与MOSFET有关的两个主要失效模式是热载流子效应和与时间有关的介质击穿(TDDB)。一     

NMOS管热载流子衰退效应评价模型及寿命预测方法研究

热载流子是器件可靠性研究的热点之一.特别对于亚微米器件,热载流子失效是器件失效的一个最主要方面.通过对这种失效机理及其失效模型的研究,为设计和工艺提供帮助,从而有效降低由热载流子引起的电路失效,提高电路可靠性.本文主要针对几种典型工艺的栅氧厚度(例如:Tox分别为150 (A)、200 (A)、250 (A))的NMOSFET进行加速应力实验,提取寿命模型的相关参数,估算这些器件在正常工作条件下的寿命值,对亚微米工艺器件寿命进行快速评价.     

采用最佳横向变掺杂技术的LDMOS中热载流子效应的研究

本文提出了一个计算结果,分析了热载流子注入氧化层的机率与表面电场强度的关系,证实了一定条件下传统的采用最佳横向变掺杂技术的LDMOS结构会受热载流子注入氧化层的影响产生热载流子效应。进而提出了一种优化的可以削弱热载流子效应的结构,研究结果表明无需变动任何工艺,该结构就能将器件表面的电场强度从 268kV/cm 降至100kV/cm ,极大地阻抗了热载流子的发射.     

A new DC Drain-Current-Conductance method (DCCM) for thecharacterization of effective mobility (μeff) and seriesresistances (Rs, Rd) of fresh and hot-carrierstressed graded junction MOSFETs

A simple new DC technique is developed to extract the gate bias dependent effective channel mobility (u_eff) and series resistances (R_s and R_d) of graded junction n- and p-channel MOSFETs. This technique is found to be accurate and effective for devices with differing channel lengths and also for devices after nonuniform hot-carrier degradation. The parameter values extracted provide further insight into the damage mechanisms of hot-carrier stressed graded junction nMOSFETs and are usable in circuit and reliability simulation. This technique is especially useful for the optimization of hot-carrier resistant structures of submicrometer MOSFETs     

New understanding of LDD NMOS hot-carrier degradation and device lifetime at cryogenic temperatures

This work shows that the worst-case gate voltage stress condition for LDD nMOSFETs is a strong function of the channel length, drain voltage, and operating temperature. A new cross-over behavior of the worst-case gate voltage condition is reported at low temperatures. New understanding of the hot-carrier mechanisms at low temperatures is also discussed. Low temperature effects such as freeze-out are shown to have important contributions to the hot-carrier behavior at low temperatures. A trend is identified for the first time which suggests important consequences for the hot-carrier reliability of deep sub-micron channel length MOSFETs under normal operating temperatures.     

Logic synthesis for reliability: an early start to controllingelectromigration and hot-carrier effects

Designing reliable CMOS chips involves careful circuit design, with attention directed to some of the potential reliability problems such as electromigration and hot-carrier effects. This paper considers logic synthesis to optimize, early in the design phase, against electromigration and hot-carrier degradation. The electromigration and hot-carrier effects are estimated at the gate level using signal activity measure (average number of transitions at circuit nodes). Results on MCNC synthesis benchmarks show that logic can be synthesized to optimize for higher reliability and lower silicon area. A minimum-area circuit is usually not associated with highest reliability     

HOT-CARRIER RELIABILITY IN n-MOSFETs USED AS PASS-TRANSISTORS

AC stressing is investigated to determine the hot-carrier reliability in a 0.5 μm CMOS technology and is interpreted by a quasi-static model based on distinct damage mechanisms. The hot-carrier dependence of n-MOSFETs operating in pass-transistor configurations is carefully studied as a function of the propagation time and geometry. It is shown that device degradation may exhibit in some cases a strong dependence on the propagation time and clearly differs from the simple case of inverter operation.     

Performance and reliability comparison between asymmetric andsymmetric LDD devices and logic gates

The performance and reliability of NMOSFET asymmetric lightly doped drain (LDD) devices (with no LDD on the source side) are compared with those of conventional LDD devices. At a fixed V_dd, asymmetric LDD devices exhibit higher I_dsat and shorter hot-carrier lifetime. To maintain the same hot-carrier lifetime, asymmetric LDD devices must operate at lower V_dd while higher I_dsat is retained. For the same hot-carrier lifetime, ring oscillators with NMOSFET asymmetric LDD devices can achieve 5% (10% if PMOSFET also had asymmetric LDD) higher speed and 10% lower power. The hot-carrier reliability of inverter, NAND, and NOR structures with asymmetric and conventional LDD devices is also simulated and compared     

Design considerations for CMOS digital circuits with improvedhot-carrier reliability

The hot-carrier induced degradation of the transient circuit performance in CMOS digital circuit structures is investigated and modeled. Delay-time degradation as a result of transistor aging, as opposed to current degradation, is devised as a more realistic measure of long-term circuit reliability. It is shown that for a wide class of circuits, the performance degradation due to dynamic hot-carrier effects can be expressed as a function of the nMOS and pMOS transistor channel widths, and the output load capacitance. In addition, the influence of the parasitic gate-drain overlap capacitance and the resulting drain voltage overshoot upon aging characteristics is investigated. The degradation of tapered (scaled) inverter chains is modeled, and a simple design guideline based on the scaling factor (F) and the transistor aspect ratio (τ) is presented for the improvement of long-term reliability in scaled buffer structures with respect to hot-carrier induced device aging. Also, a number of simple design rules based on device geometry, circuit topology and power supply voltage are presented to ensure hot-carrier reliability