Geometrical effects in high current gain 1100-V 4H-SiC BJTs

This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain /spl beta/=64 and a breakdown voltage of 1100 V. The high /spl beta/ value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The BJTs show a clear emitter-size effect indicating that surface recombination has a significant influence on /spl beta/. A minimum distance of 2-3 /spl mu/m between the emitter edge and base contact implant was found adequate to avoid a substantial /spl beta/ reduction.     

High-voltage implanted-emitter 4H-SiC BJTs

Implanted-emitter, epi-base, npn 4H-SiC bipolar junction transistors (BJTs) which show maximum blocking voltage of 500 V and common-emitter current gain (β) of 8 are demonstrated. Compared to the previous results (BV_CEO of 60 V and β of 40), the blocking voltage is greatly improved with reduced current gain due to a decrease of the base transport factor. The samples also show negative temperature coefficient of β, similar to the previous samples, easing device paralleling problems     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

High voltage (>1kV) and high current gain (32) 4H-SiC power BJTs using Al-free ohmic contact to the base

This letter reports the design and fabrication of 4H-SiC bipolar junction transistors with both high voltage (>1kV) and high dc current gain (/spl beta/=32) at a collector current level of I/sub c/=3.83A (J/sub c/=319 A/cm/sup 2/). An Al-free base ohmic contact has been used which, when compared with BJTs fabricated with Al-based base contact, shows clearly improved blocking voltage. A specific on-resistance of 17 m/spl Omega//spl middot/cm/sup 2/ has been achieved for collector current densities up to 289 A/cm/sup 2/.     

High current gain 4H-SiC npn bipolar junction transistors

The authors report a common emitter current gain /spl beta/ of 55 in npn epitaxial-emitter 4H-SiC bipolar junction transistors. The spacing between the p+ base contact implant and the edge of the emitter finger is critical in obtaining high-current gain. V/sub CEO/ of these devices is 500 V, and V/sub CBO/ is 700 V.     

Spatial nonuniformity of 4H-SiC avalanche photodiodes at high gain

We report spatial nonuniformity of responsivity of 4H-SiC avalanche photodiodes at high gain (M > 1000) that results from variation in the doping density. Two-dimensional raster scans show a steady decline laterally across the device. The direction in which the spatial response decreases is the same as that of increasing breakdown voltage on the wafer.     

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

一种新型4H-SiC BJT结终端结构研究

设计了一种应用于4H-SiC BJT的新型结终端结构。该新型结终端结构通过对基区外围进行刻蚀形成单层刻蚀型外延终端,辅助耐压的p+环位于刻蚀型外延终端的表面,采用离子注入的方式,与基极接触的p+区同时形成。借助半导体数值分析软件SILVACO,对基区外围的刻蚀厚度和p+环的间距进行了优化。仿真分析结果表明,当刻蚀厚度为0.8μm,环间距分别为8,10和9μm时,能获得最高击穿电压。新结构与传统保护环(GR)和传统结终端外延(JTE)相比,BVCEO分别提高了34%和15%。利用该新型终端结构,得到共发射极电流增益β>47、共发射极击穿电压BVCEO为1 570V的4H-SiC BJT器件。     

8000-V 1000-A gate turn-off thyristor with low on-state voltage andlow switching loss

An 8 kV, 1 kA gate turn-off thyristor (GTO) that has been designed with a combination of a p-i-n structure and a ringed-anode short structure is discussed. The GTO has been fabricated using a diffusion and epitaxial buffer process. As a consequence, low on-state voltage and low switching loss have been achieved, solving the two major problems in high-voltage GTOs. The device's structure, the p-i-n base process, and the electrical characteristics of the GTO are described     

1200-V 5.2-mΩ·cm2 4H-SiC BJTs With a High Common-Emitter Current Gain

This letter presents fabrication of a power 4H-SiC bipolar junction transistor (BJT) with a high open-base breakdown voltage BV_CEO ap 1200 V, a low specific on-resistance R _{SP_ON} ap 5.2 mOmegamiddotcm², and a high common-emitter current gain beta ap 60. The high gain of the BJT is attributed to reduced surface recombination that has been obtained using passivation by thermal silicon dioxide grown in nitrous oxide (N₂O) ambient. Reference BJTs with passivation by conventional dry thermal oxidation show a clearly lower current gain and a more pronounced emitter-size effect. BJTs with junction termination by a guard-ring-assisted junction-termination extension (JTE) show about 400 V higher breakdown voltage compared with BJTs with a conventional JTE.     

Drift-free 10-kV, 20-A 4H-SiC PiN diodes

As impressive as the advancement in 4H-SiC material quality has been, 4H-SiC PiN diodes continue to suffer from irreversible, forward-voltage instabilities. In this work, we describe PiN diodes designed to block 10 kV and conduct 20 A at less than 4.5 V, which were fabricated on 4H-SiC PiN epitaxial layers that were grown with an innovative epitaxial process that has been developed specifically to suppress V_F drift. The diodes fabricated on epitaxial layers that implemented this new epitaxy process showed excellent V_F stability, with 86% of the diodes drifting less than 0.1 V during forward current stressing at 10 A (50 A/cm²) for 30 min. However, these improvements in V_F drift come with a cost in blocking yield, as the surface morphology and other crystal defects imparted by the epitaxial process resulted in only 1 of 50 diodes reaching the 10-kV blocking specification. Nevertheless, the remarkable progress in V_F drift yield brings us closer to commercialization of high-power 4H-SiC PiN diodes.     

700-V asymmetrical 4H-SiC gate turn-off thyristors (GTO's)

Silicon Carbide (4H-SiC), asymmetrical gate turn-off thyristors (GTO's) were fabricated and tested with respect to forward voltage drop (V_F), forward blocking voltage, and turn-off characteristics. Devices were tested from room temperature to 350°C in the dc mode. Forward blocking voltages ranged from 600-800 V at room temperature for the devices tested. V_F of a typical device at 350°C was 4.8 V at a current density of 500 A/cm². Turn-off time was less than 1 μs. Although no beveling or advanced edge termination techniques were used, the blocking voltage represented approximately 50% of the theoretical value when tested in an air ambient. Also, four GTO cells were connected in parallel to demonstrate 600-V, 1.4 A (800 A/cm ²) performance     

Enhanced current gain in SiC power BJTs using a novel surface accumulation layer transistor concept

In this paper, we demonstrate that the current gain of SiC power bipolar transistors can be improved by as large as 100% by using a novel surface accumulation layer transistor concept in which a reflecting boundary in the emitter reduces the base current. The reasons for the improved current gain are explained based on simulation results.     

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N⁺ source implantation. High dose N⁺ implantation requires high-temperature (1550 °C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850 °C for 5 min exhibit a high peak field-effect mobility (μ_FE) of 95 cm²/V s at room temperature (25 °C) and 255 cm²/V s at 200 °C with stable normally-off operation from 25 °C to 200 °C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.     

Design considerations for 12-V/1.5-V, 50-A voltage regulatormodules

The paper presents design considerations for a 12-V/1.5-V, 50-A voltage regulator module (VRM) for the next generation of microprocessors. The module has stringent power-density and transient-response specifications, which are hard to meet with traditional design techniques. The proposed design solutions increase the VRM efficiency, as well as achieve the desired transient response with a minimum amount of the output capacitance     

Record gain at 3.1 GHz of 4H-SiC high power RF MESFET

In this paper, a very high gain 4H-SiC power MESFET with incorporation of L-gate and source field plate (LSFP-MESFET) structures for high power and RF applications is proposed. The influence of L-gate and source field plate structures on saturation current, breakdown voltage (V_b) and small-signal characteristics of the LSFP-MESFET was studied by numerical device simulation. The optimized results showed that V_b of the LSFP-MESFET is 91% larger than that of the 4H-SiC conventional MESFET (C-MESFET), which meanwhile maintains almost 77% higher saturation drain current characteristics. The maximum output power densities of 21.8 and 5.5 W/mm are obtained for the LSFP-MESFET and C-MESFET, respectively, which means about 4 times larger output power for the proposed device. Also, the cut-off frequency (f_T) of 23.1 GHz and the maximum oscillation frequency (f_max) of 85.3 GHz for the 4H-SiC LSFP-MESFET are obtained compared to 9.4 and 36.2 GHz for that of the C-MESFET structure, respectively. The proposed LSFP-MESFET shows a new record maximum stable gain exceeding 22.7 dB at 3.1 GHz, which is 7.6 dB higher than that of the C-MESFET. To the best of our knowledge, this is 2.5 dB greater than the highest gain yet reported for SiC MESFETs, showing the potential of this device for high power RF applications.     

600- and 1200-V bipolar-mode MOSFET's with high current capability

600-V 25-A and 1200-V 20-A bipolar-mode MOSFET's (T-BIFET) with 100-A and 75-A maximum current capability, respectively, have been developed, based on a new pattern design theory for high latch-up current density. It is also shown than an n⁺-buffer layer improves a tradeoff between the forward voltage and the turn-off time, compared with an ordinary n-buffer layer.     

1300-V 6H-SiC lateral MOSFETs with two RESURF zones

A two-zone, lateral RESURF field 6H-SiC MOSFET with breakdown voltage as high as 1300 V and specific on-resistance of 160 m/spl Omega//spl middot/cm/sup 2/ has been fabricated. These MOSFETs exhibit stable and reversible breakdown indicating avalanche breakdown in SiC that has not been reported in earlier lateral SiC MOSFETs.