Geometrical effects in high current gain 1100-V 4H-SiC BJTs

This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain /spl beta/=64 and a breakdown voltage of 1100 V. The high /spl beta/ value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The BJTs show a clear emitter-size effect indicating that surface recombination has a significant influence on /spl beta/. A minimum distance of 2-3 /spl mu/m between the emitter edge and base contact implant was found adequate to avoid a substantial /spl beta/ reduction.     

High-voltage implanted-emitter 4H-SiC BJTs

Implanted-emitter, epi-base, npn 4H-SiC bipolar junction transistors (BJTs) which show maximum blocking voltage of 500 V and common-emitter current gain (β) of 8 are demonstrated. Compared to the previous results (BV_CEO of 60 V and β of 40), the blocking voltage is greatly improved with reduced current gain due to a decrease of the base transport factor. The samples also show negative temperature coefficient of β, similar to the previous samples, easing device paralleling problems     

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.     

High current density 800-V 4H-SiC gate turn-off thyristors

4H-SiC gate turn-off thyristors (GTOs) were fabricated using the recently developed inductively-coupled plasma (ICP) dry etching technique. DC and ac characterisation have been done to evaluate forward blocking voltage, leakage current, on-state voltage drop and switching performance. GTOs over 800 V dc blocking capability has been demonstrated with a blocking layer thickness of 7 μm. The dc on-state voltage drops of a typical device at 25 and 300°C were 4.5 and 3.6 V, respectively, for a current density of 1000 A/cm². The devices can be reliably turned on and turned off under an anode current density of 5000 A/cm² without observable degradation     

高电流增益的碳化硅双极型晶体管

A novel 4H-SiC BJT of high current gain with a suppressing surface traps effect has been proposed. It is effective to improve the current gain due to the lower electrons density in the surface region by extending the emitter metal to overlap the passivation layer on the extrinsic base surface. The electrons trapped in the extrinsic base surface induce the degeneration of Si C BJTs device performance. By modulating the electron recombination rate, the novel structure can increase the current gain to 63.2% compared with conventional ones with the compatible process technology. Optimized sizes are an overlapped metal length of 4 m, as well as an oxide layer thickness of 50 nm.     

High voltage (>1kV) and high current gain (32) 4H-SiC power BJTs using Al-free ohmic contact to the base

This letter reports the design and fabrication of 4H-SiC bipolar junction transistors with both high voltage (>1kV) and high dc current gain (/spl beta/=32) at a collector current level of I/sub c/=3.83A (J/sub c/=319 A/cm/sup 2/). An Al-free base ohmic contact has been used which, when compared with BJTs fabricated with Al-based base contact, shows clearly improved blocking voltage. A specific on-resistance of 17 m/spl Omega//spl middot/cm/sup 2/ has been achieved for collector current densities up to 289 A/cm/sup 2/.     

4H-SiC BJT的Early电压分析

通过考虑缓变基区4H-SiC BJT电流增益及器件内4种载流子复合过程,计算了4H-SiC BJT的厄利(Early)电压,分析了Early电压及电流增益的温度特性.结果表明,其他参数不变时,Early电压VA随发射区掺杂浓度NE增大而增大,随集电区掺杂浓度Nc增大而减小,随基区宽度W增大而增大.SiC中杂质非完全离化会影响4H-SiC BJT的Early电压及电流增益的温度特性.     

4H-SiC BJT的Early电压分析

通过考虑缓变基区4H-SiC BJT电流增益及器件内4种载流子复合过程,计算了4H-SiC BJT的厄利(Early)电压,分析了Early电压及电流增益的温度特性.结果表明,其他参数不变时,Early电压VA随发射区掺杂浓度NE增大而增大,随集电区掺杂浓度Nc增大而减小,随基区宽度W增大而增大.SiC中杂质非完全离化会影响4H-SiC BJT的Early电压及电流增益的温度特性.     

High current gain 4H-SiC npn bipolar junction transistors

The authors report a common emitter current gain /spl beta/ of 55 in npn epitaxial-emitter 4H-SiC bipolar junction transistors. The spacing between the p+ base contact implant and the edge of the emitter finger is critical in obtaining high-current gain. V/sub CEO/ of these devices is 500 V, and V/sub CBO/ is 700 V.     

双外延基区4H-SiC BJTs的高温特性研究

基于4H-SiC的材料特性及双外延基区BJTs的工作原理,依据漂移扩散及复合理论,求解在考虑4种复合机制下的双极晶体管直流增益,并通过二维仿真模型对其在高温条件下的工作特性进行了计算分析。结果表明,随着温度的升高,基区离化率的增加会导致发射极注入效率下降,从而降低器件的直流增益。同时,SiC/SiO2 界面态及钝化层的质量会影响器件的表面复合速度,从而造成大电流下直流增益的显著下降。     

High temperature characterization of double base epilayer 4H-SiC BJTs

Based on the material characteristics and the operational principle of the double base epilayer BJTs, and according to the drift-diffusion and the carrier recombination theory, the common emitter current gain is calculated considering four recombination processes. Then its performance is analyzed under high temperature conditions. The results show that the emitter injection efficiency decreases due to an increase in the base ionization rate with increasing temperature. Meanwhile, the SiC/SiO2 interface states and the quality of the passivation layer will affect the surface recombination velocity, and make an obvious current gain fall-off at a high collector current.     

Spatial nonuniformity of 4H-SiC avalanche photodiodes at high gain

We report spatial nonuniformity of responsivity of 4H-SiC avalanche photodiodes at high gain (M > 1000) that results from variation in the doping density. Two-dimensional raster scans show a steady decline laterally across the device. The direction in which the spatial response decreases is the same as that of increasing breakdown voltage on the wafer.     

台面结终端高压4H-SiC BJTs的击穿特性研究

根据雪崩碰撞理论,本文对具有台面结构的4H-SiC BJTs中所使用的单区和多区结终端结构参数对击穿电压的影响进行了分析和计算。计算结果表明,在单区结终端结构中,通过精确控制有源JTE的掺杂浓度和离子注入深度可以有效提高台面BJTs器件的击穿电压,而多区结终端结构可以在保持击穿电压不变的前提下降低峰值表面电场。同时文中还对正负表面态或界面态对击穿电压的影响做了详细的计算分析。这些结果对于优化台面功率器件的高压特性有着重要的现实意义。     

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.     

Characteristics of blocking voltage for power 4H-SiC BJTs with mesa edge termination

According to the avalanche ionization theory,a computer-based analysis is performed to analyze the structural parameters of single-and multiple-zone junction termination extension (JTE) structures for 4H-SiC bipolar junction transistors (BJTs) with mesa structure.The calculation results show that a single-zone JTE can yield high breakdown voltages if the activated JTE dose and the implantation width are controlled precisely and a multiple-zone JTE method can decrease the peak surface field while still maintaining a high blocking capability.The influences of the positive and negative surface or interface states on the blocking capability are also shown.These conclusions have a realistic meaning in optimizing the design of a mesa power device.     

On the assessment of few design proposals for 4H-SiC BJTs

A theoretical design analysis using two-dimensional numerical computer aided design tool (TCAD) is presented for 4H-SiC BJTs. Compared to conventional design, a high p-doped thin layer between the base–emitter region is effective to suppress the surface recombination between the base–emitter region. Using a surface recombination layer (SR layer of 60 nm thickness and acceptor doping of 1.0×10¹⁹ cm⁻³) between base–emitter region, a peak gain of 410 was obtained at 100 A/cm². While a second epitaxy growth run is needed to utilize the advantage of this design, an alternate design with thin high doped (i.e., delta layer design) layer at the base–emitter junction is also interesting from the point of view of improving current gain with reduced on-resistance. A delta layer design thus produces a peak current gain of 300 at 100 A/cm² and on-resistance value of 4 mΩ-cm² at 300 K. Compared to the experimental data of 4H-SiC BJTs, present simulated analysis provides superior performance in terms of current gain.     

一种新型4H-SiC BJT结终端结构研究

设计了一种应用于4H-SiC BJT的新型结终端结构。该新型结终端结构通过对基区外围进行刻蚀形成单层刻蚀型外延终端,辅助耐压的p+环位于刻蚀型外延终端的表面,采用离子注入的方式,与基极接触的p+区同时形成。借助半导体数值分析软件SILVACO,对基区外围的刻蚀厚度和p+环的间距进行了优化。仿真分析结果表明,当刻蚀厚度为0.8μm,环间距分别为8,10和9μm时,能获得最高击穿电压。新结构与传统保护环(GR)和传统结终端外延(JTE)相比,BVCEO分别提高了34%和15%。利用该新型终端结构,得到共发射极电流增益β>47、共发射极击穿电压BVCEO为1 570V的4H-SiC BJT器件。     

8000-V 1000-A gate turn-off thyristor with low on-state voltage andlow switching loss

An 8 kV, 1 kA gate turn-off thyristor (GTO) that has been designed with a combination of a p-i-n structure and a ringed-anode short structure is discussed. The GTO has been fabricated using a diffusion and epitaxial buffer process. As a consequence, low on-state voltage and low switching loss have been achieved, solving the two major problems in high-voltage GTOs. The device's structure, the p-i-n base process, and the electrical characteristics of the GTO are described     

1200-V 5.2-mΩ·cm2 4H-SiC BJTs With a High Common-Emitter Current Gain

This letter presents fabrication of a power 4H-SiC bipolar junction transistor (BJT) with a high open-base breakdown voltage BV_CEO ap 1200 V, a low specific on-resistance R _{SP_ON} ap 5.2 mOmegamiddotcm², and a high common-emitter current gain beta ap 60. The high gain of the BJT is attributed to reduced surface recombination that has been obtained using passivation by thermal silicon dioxide grown in nitrous oxide (N₂O) ambient. Reference BJTs with passivation by conventional dry thermal oxidation show a clearly lower current gain and a more pronounced emitter-size effect. BJTs with junction termination by a guard-ring-assisted junction-termination extension (JTE) show about 400 V higher breakdown voltage compared with BJTs with a conventional JTE.