基于FPGA的高性能全数字锁相环设计与实现

本文提出了一种适用范围广泛的全数字锁相环(ADPLL)实现方法,在锁相环输入频率未知的情况下,实现锁相锁频功能.本文从全数字锁相环的基本实现方式入手,进行改进,并使用VHDL语言建模,使用FPGA进行验证.     

An all-digital phase-locked loop for high-speed clock generation

An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications.     

An all-digital phase-locked loop (ADPLL)-based clock recoverycircuit

A new algorithm for all-digital phase-locked loops (ADPLL) with fast acquisition and large pulling range is presented in this paper. Based on the proposed algorithm, portable cell-based implementations for clock recovery with functions of a frequency synthesizer and on-chip clock generator are completed by standard cell. These modules have been designed and verified on a 0.6-μm CMOS process. Test results are summarized as follows: 1) the proposed ADPLL can satisfy full locked bandwidth and fast acquisition within one data transition; 2) the on-chip clock generator can generate any target clock rate f_clock ; and 3) the function of nonreturn-to-zero clock recovery has a maximum f_clock/4 recovering capability with a locking range of (τ_input±τ_input/2)) where τ _input is the input period     

A low power time-to-digital converter for all-digital phase-locked loop

Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL’s total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.     

A new all-digital phase-locked loop with high precision and low jitter

A new method is proposed in this article to accomplish the fine tune unit of the digitally controlled oscillator of an all-digital phase-locked loop (ADPLL). Instead of using adjustable currents, we utilise the difference of the equivalent capacitance obtained from the drain of MOS transistors between on and off states as the fine tune delay parameter. Based on post-layout simulation results, the time resolution of the fine tune delay element can achieve results as good as 1.7126 ps. The operating frequency of this presented ADPLL ranges from 308 to 587 MHz. As compared to prior arts, the power consumption per MHz is reduced over 15% and the jitter is as low as 5 ps, which is a significant improvement.     

An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time

An all-digital phase-locked loop (PLL) circuit in which resolution in the phase detector and digitally controlled oscillator (DCO) exactly matches the gate-delay time is presented. The pulse delay circuit is connected in a ring shape with 32 inverters (2/sup 5/ inverters). With the inverter gate-delay time as the time base, the pulse phase difference is detected simultaneously with the generation of the output clock. In this system, the phase detector and oscillator share a single ring-delay-line (RDL). This means the resolution is the same at all times, making a high-speed response possible. In a prototype integrated circuit (IC) using 0.65-/spl mu/m CMOS, the generation of a frequency multiplication clock was achieved with four reference clocks, and that of a phase-locked clock with seven reference clocks, for a high-speed response. The cell size was 1.08 /spl times/ 1.08 mm/sup 2/, and the output clock frequency had a wide range of 50 kHz/spl sim/60 MHz. The multiplication range of the clock frequency was also a very wide 4/spl sim/1022, and a high level of precision was achieved with a clock jitter standard deviation of 234 ps. This digital PLL can withstand a broad range of operating environments, from -30/spl deg/C/spl sim/140/spl deg/C, and is suitable for making a programmable clock generator on a chip.     

应用于SoC的全数字锁相环ASIC设计

设计了一种全数字锁相环(All-Digital PLL).该锁相环中环形数控振荡器由使能单元构成,且环形结构分为粗调和精调两部分,具有锁定范围宽、锁定精度高、功耗低的特点,且捕获范围可以根据需要进一步拓宽.本设计基于CMOS标准单元,所有子模块均采用可综合的Verilog HDL代码描述,利于不同工艺问的移植,设计周期...     

一种新型宽频域全数字锁相环的研究与设计

针对传统锁相环研究中电路结构复杂、鉴相精度不高、锁相范围窄等问题,提出一种新型全数字锁相环。与传统锁相环相比,鉴相模块中的时间数字转换电路能将鉴相误差转换为高精度数字信号,一种双边沿触发的数字环路滤波器取代了传统的数字环路滤波器的电路结构,采用可变模分频器来替换传统的固定模分频器。应用EDA技术完成了系统设计,并采用QuartusⅡ软件进行了系统仿真验证。仿真结果表明:该锁相环锁相范围约为800 Hz~1 MHz,系统锁定时间最快为10个左右输入信号周期,且具有锁相范围大、精度高、电路结构简单和易于集成等特点。     

Design of a digital FM demodulator based on a 2nd-order all-digital phase-locked loop

Software-defined radio (SDR) is a revolution in radio design due to the ability to create radios that can self-adapt on the fly. In SDR devices, all of the signal processing is implemented in the digital domain, mainly on DSP blocks or by DSP software. By simply downloading a new program, a SDR device is able to interoperate with different wireless protocols, incorporate new services, and upgrade to new standards. Therefore, massively parallel signal processing at higher frequencies are needed to implement a realistic SDR. Thus, FPGAs have been used extensively for implementing essential functions in SDR architectures at lower frequencies. In this paper, we explore the design of a digital FM receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL). The circuit is designed in VHDL, then synthesized and simulated using LeonardoSpectrum Level 3 and ModelSim SE 6, respectively. It operates at a frequency up to 150 MHz and occupies the area of roughly 15 K logic gates.     

An optimum phase-locked loop with a non-ideal filter

In communications engineering the problem of synchronization is vital. Any loss of synchronism is required to be restored in the shortest possible time. The concept of optimum PLL which utilizes a non-linear, memoryless feedback device was introduced by Ahmed and Cheng (1974). It was shown that this optimum PLL achieves synchronization in the minimum time if the filter were ideal.

This paper considers the optimization of the PLL with non-ideal filter. The input sinusoid and the VCO output are assumed to have the same frequency but to differ in phase. The object of this paper is to investigate whether the optimum PLL introduced earlier (Ahmed and Cheng, p. 254) still retains its virtues when the ideal filter is replaced by a non-ideal one.

The nonlinear Volterra integro-differential equation governing the PLL performance is solved by two different approaches and the solution indicates that the PLL in the presence of a non-ideal filter is optimal only within a certain range of variation of the parameter defining the non-linear device.     

80 Gbit/s optical clock recovery with automatic lock acquisition using electrical phase-locked loop

A novel electrical phase-locked loop architecture for optical clock recovery using an input mixer mixing down to the intermediate frequency is presented. Phase detectors of the phase-locked loop operate on an intermediate frequency. The architecture allows the use of the quadrature phase detection enabling automatic lock acquisition.     

An extension of the Gill and Gupta discrete phase-locked loop

A variation of Gill and Gupta's first- and second-order discrete phase-locked loops (DPLL) is presented here. The novelty is that the sampling intervals lock at half the signal's period, enabling us to obtain a greater bandwidth and an increase in the locking speed.     

A single capacitor loop filter phase-locked loop with frequency voltage converter

A novel phase-locked loop that has a loop filter consisting of only one capacitor is designed with a frequency voltage converter (FVC). Simulation and measurement results show that the proposed phase-locked loop (PLL) works stably demonstrating that the FVC works effectively as a resistor. Measurement results of the proposed PLL fabricated in a one-poly six-metal 0.18 μm CMOS process show that the phase noise is ?109 dBc/Hz at 10 MHz offset from 752.7 MHz output frequency.     

An area-saving dual-path loop filter for low-voltage integrated phase-locked loops

This paper proposes an area-saving dual-path loop filter (LPF) for low-voltage integrated phase-locked loops (PLLs). With this LPF, output current of the lowpass-path charge-pump (CP) is B times (B>1) as great as that of the integration-path CP. By adding voltages across these two paths, the zero-capacitance is magnified B times equivalently. As a result, the chip size is greatly reduced. Based on this LPF, a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18 μm RFCMOS technology. Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that, at a frequency of 3.20 GHz, phase noise is -120.2 dBc/Hz at 1 MHz offset, reference spur is -72 dBc, and power is 24 mW.     

一种用于低电压集成锁相环的省面积的双通道环路滤波器

This paper proposes an area-saving dual-path loop filter（LPF）for low-voltage integrated phase-locked loops（PLLs）.With this LPF,output current of the lowpass-path charge-pump（CP）is B times（B〉1）as great as that of the integration-path CP.By adding voltages across these two paths,the zero-capacitance is magnified B times equivalently.As a result,the chip size is greatly reduced.Based on this LPF,a 1.2 V 3.5 GHz-band PLL is fabricated in SMIC 0.18μm RFCMOS technology.Its zero-capacitance is only 1/30 of that in conventional second-order LPFs. Measured data show that,at a frequency of 3.20 GHz,phase noise is–120.2 dBc/Hz at 1 MHz offset,reference spur is–72 dBc,and power is 24 mW.     

A monolithic phase-locked loop with post detection processor

Describes the design and fabrication of a high-frequency (50-MHz) phase-locked loop with a post detection processor which allows the detection of FSK signals with few external components. The circuit operates with a single 5-V supply and has TTL compatible inputs and outputs.     

A low-noise fast-lock phase-locked loop with adaptive bandwidthcontrol

This paper presents a salient analog phase-locked loop (PLL) that adaptively controls the loop bandwidth according to the locking status and the phase error amount. When the phase error is large, such as in the locking mode, the PLL increases the loop bandwidth and achieves fast locking. On the other hand, when the phase error is small, this PLL decreases the loop bandwidth and minimizes output jitters. Based on an analog recursive bandwidth control algorithm, the PLL achieves the phase and frequency lock in less than 30 clock cycles without pre-training, and maintains the cycle-to-cycle jitter within 20 ps (peak-to-peak) in the tracking mode. A feed forward-type duty-cycle corrector is designed to keep the 50% duty cycle ratio over all operating frequency range     

Third-order delay-locked loop: mean time to lose lock and optimalparameters

A systematic approximation for the mean time to lose lock (MTLL) of a coherent third-order PN-code tracking loop has been derived. Such loops are essential in various spread spectrum systems (Global Positioning System, for example). The computation of the MTLL is based on the singular perturbation method. The application of this method to the coherent delay-locked loop (DLL) yields an approximate expression for the MTLL. Therefore, with the proposed loop model the authors are able to analyze this third-order system at a level that gives a well understanding of the nonlinear loop behavior and the exit phenomenon. The influence of a loop offset due to an acceleration rate (jerk) between transmitter and receiver on the optimal filter parameters is described by comparing MTLL and tracking error performance. As intuitively might be expected it turns out that acceleration rate and code rate are exchangeable in the sense that a lower code rate allows a higher acceleration rate (and vice versa) for the same signal-to-noise ratio in order to maintain the same performance. In a case study, GPS code tracking for objects with high jerk is briefly discussed