Cu镀Au腔体气密性封装工艺研究

Cu镀Au腔体是微波器件常用封装载体之一。在目前应用中,Cu镀Au腔体微波器件的气密性封装一直是工程化技术难题,大幅影响了微波器件的可靠性和使用寿命。对基于Cu镀Au腔体的微波器件进行了气密性封装研究,探讨了Cu镀Au腔体实现气密性封装可能的工艺路线。通过比较激光封焊和真空钎焊等传统气密性封装工艺方法,提出了＂小孔密封...     

多层混合填充吸波材料的三目标粒子群优化

使用多层结构来离散自由空间到金属衬底之间理想的连续阻抗变化过程是吸波材料设计的重要方 法之一,较多层数的精细结构能够更好地逼近这一连续变化过程以获得更理想的吸波性能,但也会增加工程实现成 本和复杂度。因此,实际工程中往往需要在结构层数和逼近精度等诸多相互矛盾的因素之间寻求平衡。文中采用 石墨烯纳米片(GNS) / 片状羰基铁颗粒(FCI)混合填充的多层吸波材料,在由极化无关的宽带宽角吸波性能、FCI 填 充量以及最终层数这三个指标所张成的三维目标空间中,基于粒子群优化对多层吸波材料进行了优化设计。结果 显示,相比于吸波性能和磁性粒子填充量二维空间中的设计结果,在FCI 填充量仅需增加不到3. 3 wt%的情况下,即 可使所需层数下降50%并保持原有吸波能力的98%;不进行优化的GNS 填充量仅增加0. 6 wt%,层数显著减少,吸 波材料的总厚度降低了14%,综合性能也提高了27. 9%。此外,与其它不同优化策略的系统进行了对比,文中设计 为混合填充吸波材料的多目标优化提供了一定参考。     

Effect of the plasma cleaning process on plastic ball grid array package assembly reliability

Interface delamination is recognized as one of the major failures of microelectronics packaging. It can result from various factors, including stresses from mismatch of adherent materials, hygrothermal stress from the release of vapor pressure of moisture during soldering reflow process, and interface material adhesion strength. The failure mechanisms are associated with cyclic loads, temperature and moisture condition as well as interface adhesion strength degradation. This paper focuses on the evaluation of plasma cleaning on PBGA assembly, including resistance to interface delamination. Two different plasma systems, powered by radio frequency (RF) and microwave (MW) energy, are studied. The optimized plasma cleaning process parameters are obtained by surface contact angle measurements. The plasma cleaning results are also verified by scanning electron microscopy (SEM) as well as physical pull and shear tests. The test vehicles are 27/spl times/27 mm 292-ball PBGAs. The results from encapsulation peel tests, die and encapsulant pull tests, bonding wire pull tests and C-Mode SAM (C-SAM) examination are presented. It is clear that an optimal plasma cleaning process can be achieved with different plasma systems. The experimental results also demonstrate that plasma cleaning has little effect on wire bonding process and die attach pull strength for given substrates and assembly materials. In all the cases, optimal plasma cleaning steps improve PBGA resistance against interface delaminations for cases where plasma cleaning is carried out before encapsulation process. Moreover, different plasma cleaning techniques would affect the assembly productivity, investment and yield. This paper demonstrates that the optimized plasma cleaning process would enhance PBGA package qualification level and improve the process yields and productivity.     

GaAs单片电路封装

简述了微波在封装中的传输特性，以及不同封装型式和材料的ＧａＡｓＭＭＩＣ封装，介绍了多层共烧陶瓷在ＭＭＩＣ封装中的应用。最后，综述了国外ＧａＡｓＭＭＩＣ的最新封装与互连技术。     

Localized bonding processes for assembly and packaging of polymeric MEMS

Localized bonding schemes for the assembly and packaging of polymer-based microelectromechanical systems (MEMS) devices have been successfully demonstrated. These include three bonding systems of plastics-to-silicon, plastics-to-glass, and plastics-to-plastics combinations based on two bonding processes of localized resistive heating: 1) built-in resistive heaters and 2) reusable resistive heaters. In the prototype demonstrations, aluminum thin films are deposited and patterned as resistive heaters and plastic materials are locally melted and solidified for bonding. A typical contact pressure of 0.4 MPa is applied to assure intimate contact of the two bonding substrates and the localized bonding process is completed within less than 0.25 s of heating. It is estimated that the local temperature at the bonding interface can reach above 150/spl deg/C while the substrate temperature away from the heaters can be controlled to be under 40/spl deg/C during the bonding process. The approach of localized heating for bonding of plastic materials while maintaining low temperature globally enables direct sealing of polymer-based MEMS without dispensing additional adhesives or damaging preexisting, temperature-sensitive substances. Furthermore, water encapsulation by plastics-to-plastics bonding is successfully performed to demonstrate the capability of low temperature processing. As such, this technique can be applied broadly in plastic assembly, packaging, and liquid encapsulation for microsystems, including microfluidic devices.     

Molecular basis of the interphase dielectric properties of microelectronic and optoelectronic packaging materials

High frequency microelectronic and optoelectronic device packaging requires the use of substrate and encapsulation materials having a low dielectric constant, low dielectric loss and high volume resistivity. Most packaging materials are polymer-ceramic composites. A clear understanding of the broadband dielectric properties of composite materials is thus of great current importance for the effective development of high frequency packaging materials and optimized package design. Toward this goal, a general framework for understanding the dielectric properties of packaging materials was recently developed in which the dielectric constant of polymer-ceramic composite materials is characterized by the electrical properties of the polymer phase, the filler phase and an interphase region within the composite system. However, for this framework to be a viable tool for tailoring the dielectric properties of packaging materials, one must understand the dielectric properties of the polymer-filler interphase region, which represents a region of polymer surrounding and bonded to the surface of each filler particle having unique dielectric and physical characteristics. This work presents a model to explain and predict the dielectric properties of the composite interphase region based on dipole polarization theory.     

柔性有机发光器件封装材料气体渗透率的质谱法测量

柔性有机电致发光器件(FOLED)封装材料的研究已成为目前国内外FOLED研究的热点。如何测量水蒸汽、氧气和其他活性气体对FOLED封装材料的渗透率, 是FOLED封装材料研究的一个重要课题。提出用质谱分析技术解决柔性有机电致发光器件封装材料气体渗透率的测量问题, 建立了一个封装材料渗透率的质谱法测量系统。介绍了该系统的原理, 利用该系统测量了水蒸汽、氧气和二氧化碳等气体对PET塑料, 以及水蒸汽对ITO薄膜、银薄膜等材料的渗透率。所获得的实验结果与其他文献报道的数据进行了比较, 证明质谱法测量的结果是可信的。     

System on Wafer: A New Silicon Concept in SiP

System integration is clearly a driving force for innovation in packaging. The need for miniaturization has led to new architectures that combine disparate technologies and materials. Today several different approaches have been developed. These include technologies like system in package. In this way, a new concept for heterogeneous integration is currently being developed at CEA-LETI and is called system on wafer (SoW). This concept is based on a chip to wafer approach. Every component is achieved by using wafer-level technologies, and the final system is performed by single component mounting on a silicon substrate. The main strength of this approach is to use silicon as a substrate for components and for basic support. To perform the SoW, a generic technological toolbox is needed. This includes every standard packaging technology such as flip chip, signal rerouting, and passive component integration as well as new advanced technologies such as microelectromechanical systems packaging, advanced interconnections, energy source integration, integrated cooling, or silicon through vias. In this paper, the SoW concept will be presented and the generic toolbox for SoW achievement will be described.      

Recent advances in plastic packaging of flip-chip and multichipmodules (MCM) of microelectronics

The success in consumer electronics in the 1990's will be focused on low-cost and high performance electronics. Recent advances in polymeric materials (plastics) and integrated circuit (IC) encapsulants have made high-reliability very-large-scale integration (VLSI) plastic packaging a reality. High-performance polymeric materials possess excellent electrical and physical properties for IC protection. With their intrinsic low modulus and soft gel-like nature, silicone gels have become very effective encapsulants for larger, high input/output (I/O) (in excess of 10 000), wire-bonded and flip-chip VLSI chips. Furthermore, the recently developed silica-filled epoxies underfills, with the well controlled thermal coefficient of expansion (TCE), have enhanced the flip-chip and chip-on-board, direct chip attach (DCA) encapsulations. Recent studies indicate that adequate IC chip surface protection with high-performance silicone gels and epoxies plastic packages could replace conventional ceramic hermetic packages. This paper will review the IC technological trends, and IC encapsulation materials and processes. Special focus will be placed on the high-performance silicone and epoxy underfills, their chemistries and use as VLSI device encapsulants for single and multichip module applications     

Plastic packaging is highly reliable

Plastic encapsulation is now a high reliability (HiRel) method of packaging active semiconductor devices and microelectronics in general. This paper shows that the traditional requirement for hermetic packaging can be overturned in favor of plastic packaging, on the following grounds: the full range of laboratory evidence of HiRel silicone junction coated IC undertaken by many researchers, showing that plastic encapsulations can now be used for microelectronics and optoelectronics in telecommunication, automotive, military and space applications as the better option in many instances; the inadequacy of the Mil-Std hermeticity specification; the demonstrated field failures of Mil-Std-883 hermetic packaged devices and the massive ingress of moisture, which caused many failures of telecommunication switching systems; and the demonstrated better field-reliability in rural tropical climates, of assessed, standard PEM from major manufacturers     

Design issues of a three-dimensional packaging scheme for power modules

This paper presents design issues of a novel three-dimensional packaging approach for power modules. Solder interconnections are implemented on power devices (insulated gate bipolar transistors and diodes) to obtain vertical interconnections for the proposed multi-layer packaging technique. Issues related to materials selection and processing, electrical and thermo-mechanical aspects of implementing the new packaging concept are discussed.     

热电式MEMS微波功率传感器的封装研究

为了研究热电式MEMS微波功率传感器封装后的性能,提出了一种COB技术的封装方案。首先,采用有限元仿真软件HFSS仿真封装前后的微波特性;然后,基于GaAs MMIC技术对热电式MEMS微波功率传感器进行制备,并对制备好的芯片进行封装。最后,对封装前后传感器的微波特性及输出特性进行测试。实验结果表明,在8～12 GHz频率范围内,封装后回波损耗小于-10.50 dB,封装前的灵敏度为0.16 mV/mW@10 GHz,封装后的灵敏度为0.18 mV/mW@10 GHz。封装后的热电式微波功率传感器输出电压与输入功率仍有良好的线性度。该项研究对热电式MEMS微波功率传感器封装的研究具有一定的参考价值和指导意义。     

Effect of mode-stirrer configurations on dielectric heating performance in multimode microwave applicators

In this paper, several mode-stirrer configurations are compared in order to establish their influence on the electric-field uniformity within an irradiated dielectric sample inserted in a microwave-heating applicator. Two different scenarios are evaluated with metallic sheets moving inside the multimode applicator. The different stirrer configurations are tested and compared for low-, medium-, and high-loss dielectric sample materials. Additionally, a straightforward procedure based on a generalized plane-wave approach is proposed and evaluated as a computationally efficient alternative for calculating the electric-field distribution inside materials processed in these microwave applicators with mode stirrers. Although very different electric patterns are achieved depending on stirrer geometry and sample permittivity, the plane-wave approach has been shown to provide a very good approximation for medium and high lossy dielectric materials.     

Simulations and experiments of three-dimensional paddle shift for IC packaging

Paddle shift is one of the most serious defects which may arise during the IC encapsulation of leadframe-type packages. The term “paddle shift” means the deflection of the leadframe-pad and die as a result of the pressure difference between the top and bottom mold cavities. In extreme cases, paddle shift could lead to a substantial reduction in the reliability of package.This paper employed a computational approach to predict the paddle shift quantity during the IC packaging process. The approach was based on precise finite element (FE) models and flow-structure decoupled analyses. Two kinds of FE models were needed for the decoupled analyses, namely a 3D FE model for the mold filling analysis (i.e. fluid-flow mesh) and a 3D FE model for the structural analysis (i.e. paddle mesh). The aim of the mold filling analysis was to identify the pressure distribution acting on the paddle structure during the encapsulation process, while the objective of the structural analysis was to determine the amount of paddle shift which was caused by pressure distribution.To investigate the relationship between the package geometry and the amount of paddle shift, the present simulations considered six TQFP (Thin quad flat package) models with different geometrical parameters. The simulation results for the paddle shift were compared with the experimental results to demonstrate the accuracy of the proposed numerical approach. It was found that a good agreement exists between the two sets of results.     

Prediction of crack growth in IC passivation layers

The aluminium interconnect structures of ICs consists of materials with a large difference in the coefficient of thermal expansion (CTE). The IC backend and packaging processes are characterized by many temperature differences that will generate thermo-mechanical stresses in these interconnect structures. The resulting stress levels can lead to crack propagation in the brittle dielectric and passivation layers. To investigate the sensitivity to crack propagation in these materials, finite element simulations are performed using a J-integral approach. The J-integral approach is used to predict the crack stability for different crack lengths, positions and directions. The obtained results with respect to critical initial cracks match with field observations in actual IC interconnect structures.     

温变参数材料微波加热的数值模拟

针对一般材料的介电参数等温度的函数，本文提出了一个微波加热分析的非线性模型。该模型基于交替迭代法求解描述加热过程的非线性耦合电磁学，热学微分方程组，通过若干数值分析的实例，说明了该方法可作为微波加热精确分析的一个有效方法。     

高压大功率芯片封装的散热研究与优化设计

针对单片高压功率集成电路芯片,利用Flo THERM软件,建立三维结构的封装模型,并对各模型进行了仿真。研究了在不同基片材料、不同粘结层材料、不同封装外壳条件下封装模型的温度变化情况,分析得出一个最优的封装方案。结果表明,当基片材料采用BeO陶瓷、粘结层采用AuSn20合金焊料、封装外壳采用金属Cu时,该封装模型的温度最低、散热效率最高。     

Resolution of Near-Field Microwave Target Detection and Imaging by Using Flat LHM Lens

It is demonstrated in this paper that higher focusing resolution will be provided by flat left-handed metamaterial (LHM) lens if compared to convex dielectric lens and elliptical reflector focusing system. High-resolution near-field microwave target detection and imaging with flat LHM lens can be implemented by scanning the focal point of the flat LHM lens in the region under detection and screening directly the field intensity distribution of backscattered microwave refocused by the flat LHM lens. Numerical simulations demonstrate that sub-wavelength imaging resolution can be obtained by the proposed approach due to the sub-wavelength focusing resolution of flat LHM lens. Moreover, almost unique imaging resolution for the detection and imaging of target at different depths is also demonstrated. For practical LHM lenses, it is shown that the losses of LHM up to the order as reported in some LHM experiments will limit the sub-wavelength resolution of the proposed approach to an acceptable level.     

High-density 3-D packaging technology based on the sidewall interconnection method and its application for CCD micro-camera visual inspection system

High-density three-dimensional (3-D) packaging technology for a charge coupled device (CCD) micro-camera visual inspection system module has been developed by applying high-density interconnection stacked unit modules. The stacked unit modules have fine-pitch flip-chip interconnections within Cu-column-based solder bumps and high-aspect-ratio Cu sidewall footprints for vertical interconnections. Cu-column-based solder bump design and underfill encapsulation resin characteristics were optimized to reduce the strain in the bump so as to achieve fine-pitch flip-chip interconnection with high-reliability. High-aspect-ratio Cu sidewall footprints were realized by the Cu-filled stacked vias at the edge of the substrate. High-precision distribution of sidewall footprints was achieved by laminating the multiple stacked unit substrates simultaneously. The fabricated high-density 3-D packaging module has operated satisfactorily as the CCD imaging data transmission circuit. The technology was confirmed to be effective for incorporating many large scale integrated (LSI) devices of different sizes at far higher packaging density than it is possible to attain using conventional technology. This paper describes the high-density 3-D packaging technology which enables all of the CCD imaging data transmission circuit devices to be packaged into the restricted space of the CCD micro-camera visual inspection system interior.     

电子材料界面裂纹的新型湿气压力模型

为了准确评估电子材料界面裂纹张开空间内的湿气压力,提出了一项新的压力计算模型。有别于传统模型,新模型充分考虑了电子材料界面裂纹扩展的物理过程,计算了湿气扩展至裂纹张开空间内的速率,并结合理想气体状态方程,推导了湿气压力与湿气扩散速率、裂纹张开度的关系。从模型的参数研究中可以发现,如果湿气对流比较缓慢或者裂纹张开度比较大,则湿气压力需要经更长的时间达到饱和。该模型的建立为界面裂纹扩展稳定性的研究,提供了湿气压力评估的理论依据和计算数值。