Excess noise measurements in ion-implanted silicon resistors

The low-frequency noise spectra of partially annealed boron-implanted silicon resistors with various geometries are measured. The implantation energies are 50, 80 and 110 keV and the doses are 2·5 × 10¹² cm^?2, 1·0 × 10¹³ cm^?2 and 1·0 × 10¹⁴ cm^?2. The spectra exhibit thermal noise and $\text{?}{}^{\mathrm{?n}}$ (excess) noise exclusively. Investigations indicate that the contracts from the implanted layer to the electrode generally contribute small amounts to the total excess noise observed. The excess noise exhibits a strong dependence on the sheet resistance of the layers, while the dependence on substrate bias, implantation energy, and on temperature is relatively weak. A discussion of the results is given in terms of a volume effect. Noise measurements on implanted layers, produced under carefully controlled conditions, show promise as a tool to investigate excess noise.     

A 3-terminal model for diffused and ion-implanted resistors

In this paper, we present a new, physically based 3-terminal model for diffused and ion-implanted resistors. The model accounts for the effects of geometry, temperature, and bias, and includes parasitic p-n junction diodes. The junction depletion capacitances are distributed to model high-frequency behavior accurately     

Popcorn noise and generation-recombination noise observed in ion-implanted silicon resistors

Experimental results show that, for low currents, the generation-recombination noise component increases with current, and, at higher currents, it decreases inversely with current. For currents greater than a certain value, a generation-recombination noise component is scarcely observed.     

Comparison of boron and neon damage effects in boron ion-implanted resistors

Boron and neon damage implants were used in fabricating integrated-circuit resistors in silicon. Resistor properties were studied as functions of damaging ion species and dose. Sheet resistances in the 10000 ?/? range were obtained with low temperature and voltage sensitivities and good d.c. isolation.     

Current noise in surface layer integrated resistors

The excess noise ratio n?1, defined as the excess noise intensity over the thermal noise intensity, is used as a parameter for characterizing the current noise of integrated resistors. Theoretically n?1 is proportional to the square of the device current, inversely proportional to the square of the device width, and independent of the device length. This is well verified by experiment. The noise spectrum is of the form $\text{1}\text{?}{}^{\mathrm{\alpha }}$ with α practically equal to unity, as expected for flicker noise. The effect of current crowding near the current-carrying contacts is investigated.     

noise measurements in ion-implanted silicon resistors as a function of the substrate reverse bias voltage

The 1/ƒ noise of ion-implanted resistors has been measured as a function of a reverse bias voltage. Using a substrate bias, the sheet-resistance was changed. It has been empirically found that the relative 1/ƒ noise is proportional to the square of the resistance.     

High-resistivity Zr resistors with Ti barrier layer for NbJosephson circuits

Zr resistors are applied to Josephson integrated circuits in place of Mo because a Zr thin film has about five times the resistivity of Mo. Zr resistors do not need to be protected during etching, unlike conventional Mo resistors, because Zr has much smaller etching rate than Nb. Zr resistors occupy only 25% of a unit cell area. Using Zr resistors reduces the area of the Josephson gate and allows increased circuit integration. Increased contact resistance between Zr and Nb films after annealing at about 350°C was found but suppressed with a Ti barrier. Resistors with a resistance variation throughout a wafer of within ±2.8% were fabricated     

The gettering of boron by an ion-implanted antimony layer in silicon

Secondary ion mass spectrometry has been employed to reveal the gettering of implanted B by an annealed, implanted Sb layer. It is shown that the gettering of B is significant, and may be caused by electric-field-enhanced diffusion of the B as well as by solubility enhancement of the electrically-active Sb. These results emphasize the first-order importance of cooperative effects between donors and acceptors in diffusion profile calculations.     

Low-frequency dispersion of transconductance in GaAs JFETs andMESFETs with an ion-implanted channel layer

An analytical model of low-frequency dispersion of transconductanced in GaAs FETs which have nonuniform profiles of carrier concentration and mobility is reported. The frequency dependence of surface charge density is incorporated into the model as a variation in the source resistance of the FETs. The model explains the low-frequency dispersion of transconductance in GaAs p-n junction FETs (JFETs) and metal-semiconductor FETs (MESFETs), both of which have a channel layer formed by ion implantation. It is suggested that the low-frequency dispersion of transconductance can be attributed to the charge exchange which occurs with the surface states in GaAs FETs     

Boron-implanted silicon resistors

The sheet resistance of silicon resistors implanted with boron at room temperature has been experimentally determined for doses from 5 × 10¹² to 2 × 10¹⁶ cm^?2. The results have been compared with the V calculated values. Two methods for minimizing the temperature coefficient, TCR, are described, and their merits and disadvantages are discussed. For a 1-kΩ/□ resistor, TCR can be reduced to 1000 ppm/°C by implanting ¹¹B⁺ at low energy, 5–10 keV, and to less than 100 ppm/°C by implanting a suitable dose of Ar⁺ damage. In a two-terminal resistor, the end effect of the total sheet resistance on TCR and on voltage coefficient VCR was also investigated.     

Model of 1/f noise in ion-implanted resistors as a function of the resistance,determined by a reverse bias voltage

A model is presented for the 1/f noise in ion-implanted resistors. The resistance was changed by a reverse bias voltage. The model explains the experimentally found square dependence between the relative 1/f noise intensity C/C_o and the relative change in resistance R/R_o.     

Nonlinear metal resistors

Rectifying I/V characteristics were observed for a thin-metal-film structure made of gold, aluminium and silver vacuum-deposited layers. Also discontinuities were found in the slope resistance of these films. The structure of the devices is described, and typical I/V and slope-resistance characteristics are presented.     

Low-frequency noise in thick-film resistors due to two-steptunneling process in insulator layer of elemental MIM cell

In this paper, it is assumed that low-frequency noise source in thick-film resistors are fluctuations of the trap occupations by electrons, tunneling through insulator layer of the elemental cell. Two conducting particles separated by a thin insulating layer form the elemental cell (MIM structure). Trap charge fluctuations are modulating the MIM cell barrier, thus modulating the tunneling current and barrier resistance. A low frequency noise model is proposed under the assumption that the space distribution of traps in thick-film resistor is symmetrical with respect to the central plane of the MIM cell. Numerical results show that in the presence of small number of traps in insulator layer of the elemental cell, 1/f noise is exhibited in a narrow frequency range (4-5 decades). A model is applied on the experimental results for noise in thick-film resistors and a method of evaluation of the trapping state's parameters is discussed based on noise measurements     

Fully ion-implanted InP/InGaAs heterojunction FET fabrication in a photodiode layer structure for monolithic integration

A fully ion-implanted InP/InGaAs HJFET has been fabricated in a layer stucture optimised for a pin photodiode. Ion implantation has been used to form the channel, to improve the source and drain contact resistances, and to define the 1.5 mu m long gate. The HJFETs show a minimum output conductance of 14 mS/mm and a maximum transconductance of 140 mS/mm.<>     

Modeling the impurity profile in an ion-implanted layer of an IGFET for the calculation of threshold voltages

An extremely simple model for the impurity profile in an ion-implanted channel layer of an IGFET is applied to simulating the substrate bias dependence of its threshold voltage. Excellent agreement is obtained between theory and experiment on n-channel silicon devices.     

Fully ion-implanted bipolar transistors

Technology for the fabrication of fully ion-implanted bipolar transistors with arsenic emitters and boron bases is described. This technology results in extremely uniform distributions of electrical parameters, e.g,, hFE= 113 with a standard deviation of 1.3 across a wafer. In addition, it can produce a wide range of doping profiles and hence, a wide range of device performance. Using very similar processing schedules, transistors with hFEfrom 20 to >5000 and with fT's from 1.5 to 8.1 GHz have been made. The features of implanted arsenic which make it an excellent emitter are: 1) it can be implanted to high doses with only a small deep side tail which has a negligible effect on the typical transistor base; 2) because of the concentration dependence of its diffusion constant, it forms a very abrupt profile after diffusion; and 3) when diffused a short distance (∼1000 Å) away from the implanted region, high-lifetime material can be incorporated into the emitter and hence, high-gain low-leakage transistors can be made. When the arsenic emitter is combined with a double-peaked boron-implanted base, precise independent control of the active and inactive base properties of the device can be achieved. This independence allows considerable latitude in the choice of device parameters for fully implanted bipolar transistors.     

Implanted high value resistors

High value resistors are desirable in integrated circuits and they can be made by ion implantation. The linearity of conventional boron implanted resistors is not, however, always satisfactory.

Methods for improving the voltage linearity of ion-implanted, integrated circuit resistors are described in this paper. In particular the use of a damaging implant was investigated in detail. Hall effect measurements as a function of temperature have shown that a deep acceptor was produced by the damage. The improved linearity observed in such layers was mainly due to the presence of this deep level, rather than to reduction of mobility. A simple theory was developed that reproduced resistor behaviour satisfactorily.

It was confirmed that the use of a known deep acceptor, such as indium, also led to improved linearity.     

电阻涂料的施工应用技术

电阻涂料的施工应用技术是电阻器生产厂家经常遇到的问题。介绍电阻涂料的涂装工艺、涂装环境、质量检查、涂膜弊病的防止、涂料组分对施工性的影响和防火安全技术 ,为国产电阻器涂料的应用提供方便。     

IC-compatible high-resistance high-voltage resistors

Previously a new high-voltage process for transistors was reported. This paper reports design, experiments, and results for high-voltage high-resistance resistors, to be utilized in compatible high-voltage integrated circuits.