An implementation of fast algorithm for elliptic curve cryptosystem over GF( p )

The design and implementation of fast algorithms related to Elliptic Curve Cryptography (ECC) over the field GF(p), such as modular addition, modular subtraction, point addition, point production, choice of embedding plaintext to a point, etc. are given. A practical software library has been produced which supports variable length implementation of the ECC-based ElGamal cryptosystem. More importantly, this scalable architecture of the design enables the ECC being used in restricted platforms as well as high-end servers based on Intel Pentium CPU. Applications such as electronic commerce security, data encryption communication, etc. are thus made possible for real time and effective ECC. Supported by the National Natural Science Foundation of China (No.60271025)     

Cellular-array modular multiplier for fast RSA public-key cryptosystem based on modified Booth's algorithm

We propose a radix-4 modular multiplication algorithm based on Montgomery's algorithm, and a fast radix-4 modular exponentiation algorithm for Rivest, Shamir, and Adleman (RSA) public-key cryptosystem. By modifying Booth's algorithm, a radix-4 cellular-array modular multiplier has been designed and simulated. The radix-4 modular multiplier can be used to implement the RSA cryptosystem. Due to reduced number of iterations and pipelining, our modular multiplier is four times faster than a direct radix-2 implementation of Montgomery's algorithm. The time to calculate a modular exponentiation is about n/sup 2/ clock cycles, where n is the word length, and the clock cycle is roughly the delay time of a full adder. The utilization of the array multiplier is 100% when we interleave consecutive exponentiations. Locality, regularity, and modularity make the proposed architecture suitable for very large scale integration implementation. High-radix modular-array multipliers are also discussed, at both the bit level and digit level. Our analysis shows that, in terms of area-time product, the radix-4 modular multiplier is the best choice.     

基于复数基的RS译码器的FPGA优化实现

研究了复数基表示GF(2^8)域元素时RS编译码问题，首先讨论了GF(2^8)域标准基与复数基之间的相互转换，然后提出了适合FPGA实现的基于复数基的并行乘法器和基于查询表法的求逆和除法算法。最后详细地讨论了基于复数基的RS译码器的FPGA实现原理和框图。     

一种基于FPGA的RS编译码器设计与实现

RS码是线性分组码中具有很强纠错能力的多进制BCH码,其在纠正随机错误和突发错误方面非常有效,因此被广泛应用于通信和数据存储系统。本文提出了一种实现复杂度低、高效率的RS编译码器实现电路,包含RS编码器、Horner准则的伴随式计算、BM算法、Chien搜索等模块,以RS(15,9)为例运用VHDL在ISE14.6软件环境下进行了功能仿真,结果与Matlab得到的理论结果一致。该方法适用于任意长度的RS编码,有着重要的应用价值。     

基于VHDL语言的有限域正则基乘法器设计

有限域的运算已经广泛应用于Reed—Solomon码、存储领域和各种加密算法中。乘法运算是其中最复杂的一种运算,有限域中的元素可以用各种基表示。文中在给出有限域元素自然基下的表示方法的基础上,推导出了域元素正则基下的表示方法,并给出了正则基下域元素的乘法运算,编写了乘法器的VHDL模型。用XILINX公司的ISE5．2软件对电路模型进行了仿真,结果表明乘法器的运算结果完全正确。     

The cryptanalysis of a public-key implementation of finite group mappings

Minghua Qu and Vanstone [2] have proposed a public-key cryptosystem (FGM) which is based on factorizations of a binary vector space (i.e., transversal logarithmic signatures of an elementary abelian 2-group). In this paper a generalized (basis-independent) decryption algorithm is given, which shows that there are many equivalent private keys, and a method of efficiently obtaining such an equivalent private key is given. The FGM cryptosystem is thus rendered insecure. Although the FGM cryptosystem is defined in terms of linear algebra, the attack given here is essentially group-theoretic in nature. Thus this attack throws doubt on any cryptosystem which relies on the security of transversal logarithmic signatures.This author was supported by S.E.R.C. Research Grant GR/H23719.     

通用快速RS编译码的设计

提出一种针对通用伽罗华域的快速RS编译码技术。该编译码技术利用了时域编码、频域译码,适用于通用的RS码本原生成表达式。分析表明,该技术与传统的时域编译码相比,复杂度明显降低,但仍具有相同的编译码能力,同时b=1本原生成表达式的RS编译码整系统的复杂度最低,仿真结果与理论分析一致。     

一种高效的可伸缩分组并行有限域乘法器及VLSI实现

文章提出了基于全1多项式基的可伸缩分组并行有限域乘法器结构，并按照最低位先入和最高位先入的方式分别进行了算法描述，分别称为AOPBLSDM（AOP-Based LSD-first Digital-Serial Multiplier）和AOPBMSDM（AOP-Based MSD-first Digital-Serial Multiplier)。该乘法器的结构规整，适于VLSI实现；同时由于该乘法器具有面积和速度可伸缩度大的特点，因而可以在不同的应用场合下找到最佳的实现方案。理论分析及ASIC综合实现结果均表明，本文所提出的结构在面积和速度上具有一定的优势。     

基于多项式基的Camellia算法S盒硬件优化

该文提出一种基于不可约多项式的Camellia算法S盒的代数表达式,并给出了该表达式8种不同的同构形式。然后,结合Camellia算法S盒的特点,基于理论证明给出一种基于多项式基的S盒优化方案,此方法省去了表达式中的部分线性操作。相对于同一种限定门的方案,在中芯国际(SMIC)130 nm工艺库中,该文方案减少了9.12%的电路面积;在SMIC 65 nm工艺库中,该文方案减少了8.31%的电路面积。最后,根据Camellia算法S盒设计中的计算冗余,给出了2类完全等价的有限域的表述形式,此等价形式将对Camellia算法S盒的优化产生积极影响。     

基于Galois域Reed-Solomon码的数据包层FEC编码软件实现

本文提出一种基于Galois域Reed-Solomon码的数据包层FEC编码软件实现方法。文中利用Galois域的运算封闭性和Reed-Solomon码的变换特笥解决了FEC编码等字长变换问题；通过查找表实现多项式运算，有效降低多项式运算的复杂度，提高了软件FEC编码的效率；文中还介绍了查找表的生成方法。实验表明，基于本文所提出的方法，能够用软件实现高效的数据包层FEC编/解码。     

非单调混沌神经元的电路实现

提出了一种非单调Ｈｏｆｉｅｌｄ型混沌神经元的电路设计，在电路中我们把轨迹状态参数的调节用可调电阻来实现，通过改变可调电阻的阻值就可以改变神经元的吸收子性质，从而可以很方便地通过实验来研究混沌神经元的动力学行为。应用该电路，我们成功地观测到了神经元的不动点、倍周期分岔和混沌现象。     

High-throughput architecture for post-quantum DME cryptosystem

Quantum computers have the potential to solve difficult mathematical problems efficiently, therefore meaning an important threat to Public-Key Cryptography (PKC) if large-scale quantum computers are ever built. The goal of Post-Quantum Cryptography (PQC) is to develop cryptosystems that are secure against both classical and quantum computers. DME is a new proposal of quantum-resistant PKC algorithm that was presented for NIST PQC Standardization competition in order to set the next-generation of cryptography standards. DME is a multivariate public key, signature and Key Encapsulation Mechanism (KEM) system based on a new construction of the central maps, that allows the polynomials of the public key to be of an arbitrary degree. In this paper, a high-throughput pipelined architecture of DME is presented and hardware implementations over Xilinx FPGAs have been performed. Experimental results show that the architecture here presented exhibits the lowest execution time and highest throughput when it is compared with other PQC multivariate implementations given in the literature.     

Design and implementation of dual-field modular inversion algorithm

Modular inverse arithmetic plays an important role in elliptic curve cryptography. Based on the analysis of Montgomery modular inversion algorithm, this paper presents a new dual-field modular inversion algorithm, and a novel scalable and unified architecture for Montgomery inverse hardware in finite fields GF(p) and GF(2 ⁿ ) is proposed. Furthermore, this architecture based on the new modular inversion algorithm has been verified by modeling it in Verilog-HDL, and accomplished it under 0.18 μm CMOS technology. The result indicates that our work has better performance and flexibility than other works.     

GF(2n)域上的一种Ⅱ型优化正规基乘法器及其FPGA实现

有限域GF(2ⁿ)上的椭圆曲线密码体制以其密钥短,安全强度高的优点正在获得广泛的重视和应用.该密码体制最主要的运算是有限域上的乘法运算.本文提出了一种基于Ⅱ型优化正规基的乘法器,该乘法器具有Massey-Omura乘法器的优点,又避免了其不足,易于编程,适合FPGA实现.实验表明,该算法简单,快速.     

An enhanced XOR‐based scheme for wireless packet retransmission problem

Solving wireless packet retransmission problem (WPRTP) using network coding (NC) is increasingly attracting research efforts. However, existing NC‐based schemes for WPRTP are with high computational complexity resulting from computation on larger Galois field (GF(2^q)), or the solutions on GF(2) found by the schemes are less efficient. In this paper, combining the basic ideas in two existing schemes, denoted as ColorNC and CliqueNC, respectively, we present a new scheme named as ColorCliqueNC. The advantages of ColorCliqueNC include the following: (i) it is suitable for all kinds of WPRTP instances; (ii) it works on GF(2); thus, it is computationally efficient than the schemes working on larger Galois fields; and (iii) the solutions found by ColorCliqueNC usually have fewer packet retransmissions than those by ColorNC and CliqueNC despite that they all work on GF(2). Theoretical analysis indicates that ColorCliqueNC is superior to ColorNC and CliqueNC. Simulation results show that ColorCliqueNC generally outperforms ColorNC and CliqueNC. Compared with ColorNC, ColorCliqueNC can save up to 10% packet retransmissions. Copyright © 2013 John Wiley & Sons, Ltd.     

快速模板匹配算法在图像循环处理中的实现

循环操作在图像处理算法中非常重要，通过对多方向模板快速算法的分析，并且结合专用硬件实现图像处理，提高了图像处理效率，节省了运行时间。     

Design and implementation of a fast algorithm for modulated lappedtransform

A new fast algorithm for the computation of the modulated lapped transform (MLT) is proposed and its efficient implementation using pipelining techniques and complex programmable logic device (CPLD) is presented. The new algorithm computes a length-M MLT via the length-M/2 fast Fourier transform (FFT). Computational overhead due to data shuffling in pre-processing and post-processing is offset in hardware realisation. Hence the overall throughput of the MLT computation for real-time applications is significantly improved. The pipelined CPLD architecture and circuitry are described in detail. Computational complexity of the proposed algorithm is analysed, and throughput improvement is verified by experimental results     

一种扩展的Rijndael算法及其DSP快速实现的研究

研究一种扩展的Rijndael算法的设计策略，重点研究了列混合变换及其逆变换的设计；在此基础上，研究列混合变换中字节模乘运算的实现算法，根据这种扩展算法加密轮的4个变换的特征，提出了两种快速实现方案。在DSP平台上实现该扩展算法的基础上，对该扩展算法的ANSI C代码进行综合优化，并取得良好的效果。另外，本文从雪崩效应角度分析了算法的安全性.     

改进的自适应去振铃滤波算法及其硬件实现

在现有去振铃滤波算法的基础上,提出了一种改进的简单易行的自适应去振铃滤波算法.在算法中,首先对图像进行边界检测,然后根据结果,对图像采取不同的窗滤波方式达到自适应滤波的效果.在本算法中,考虑了人类视觉系统的特性;同时兼顾算法硬件可实现性.在保证滤波效果的前提下,以较小的硬件代价实现了算法.     

Low power options for 32 nm always-on SRAM architecture

The SRAM 6T bit-cell suffers many limitations in advanced technology nodes among which variability effects. Various alternatives have been experimented and the paper focuses on the 5T-Portless bit-cell. Read and write operations are operated by varying voltage conditions. Literature regarding 32 nm CMOS for Portless SRAM has been reviewed and improvements are presented. The bit-cells are arranged in matrix to permit a current-mode read operation as opposed to voltage-based sensing techniques. Thus safety and stability of the bit-cell operation is established without constraints on memory periphery. The current-mode operation enables a significant gain in dynamic power consumption beneficial to always-on memories. The paper presents different existing solutions to limit the power consumption and their limitations in thin CMOS technologies. The portless bit-cell is presented as a low power architecture alternative to 6T-SRAM. A matrix test-chip is currently under fabrication in bulk CMOS 32 nm.