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1.
The electrical characteristics of HfO2-Ta2O5 mixed stacks under constant current stress (CCS) at gate injection with 20 mA/cm2 and stressing times of 50 and 200 s have been investigated. A very weak effect of the stress on the global dielectric constant, on fast and slow states in the stack as well as on the dominant conduction mechanism is detected. The most sensitive parameter to the CCS is the leakage current. The stress-induced leakage current (SILC) is voltage and thickness dependent. The pre-existing traps govern the trapping kinetics and are a key parameter to evaluate the stress response. Two processes - positive charge build-up and new bulk traps generation - are suggested to be responsible for SILC: the domination of one of them depends on both the film thickness and the stressing time. The positive charge build-up is localized close to the gate electrode implying gate-induced defects could be precursors for it. It is established that unlike the case of single SiO2 layer, the bulk traps closer to the gate electrode control SILC in the mixed Ta2O5-HfO2-based capacitors.  相似文献   

2.
The stress-induced leakage current in Hf-doped Ta2O5 layers (7; 10 nm) under constant voltage stress at gate injection was investigated in order to assess the mechanisms of conduction, the traps involved and the effect of Hf doping. The amount of Hf is found to affect the conduction mechanisms, the temperature dependence of the leakage current and the current response to the stress. A significant leakage current increase is observed only when the stress voltage and/or stress time exceed the corresponding threshold values, where the charge trapping at the pre-existing traps dominates below and defect generation above these threshold values. The energy levels of the traps responsible for the current transport are estimated. The stress effect on dominant conduction mechanisms appears quite weak, and the nature of the traps controlling the current transport before and after the stress seems to be nearly identical. The results indicate that the constant voltage stress affects the pre-existing traps in Hf-doped Ta2O5 and modifies their parameters, but there is no evidence for stress-induced generation of traps with completely new nature different from oxygen-vacancy related defects.  相似文献   

3.
The Time-Dependent-Dielectric Breakdown (TDDB) characteristics of MOS capacitors with Hf-doped Ta2O5 films (8 nm) have been analyzed. The devices were investigated by applying a constant voltage stress at gate injection, at room and elevated temperatures. Stress voltage and temperature dependences of hard breakdown of undoped and Hf-doped Ta2O5 were compared. The doped Ta2O5 exhibits improved TDDB characteristics in regard to the pure one. The maximum voltage projected for a 10 years lifetime at room temperature is −2.4 V. The presence of Hf into the matrix of Ta2O5 modifies the dielectric breakdown mechanism making it more adequate to the percolation model. The peculiarities of Weibull distribution of dielectric breakdown are discussed in terms of effect of three factors: nature of pre-existing traps and trapping phenomena; stress-induced new traps generation; interface layer degradation.  相似文献   

4.
The response of lightly Al-doped Ta2O5 stacked films (6 nm) to constant current stress (CCS) under gate injection (current stress in the range of 1 to 30 mA/cm2 and stressing time of 50–400 s) has been investigated. The stress creates positive oxide charge, which is assigned to oxygen vacancies but it does not affect the dielectric constant of the films. The most sensitive parameter to the stress is the leakage current. Different degradation mechanisms control the stress-induced leakage current (SILC) in dependence on both the stress conditions and the applied measurement voltage. The origin of SILC is not the same as that in pure and Ti- or Hf-containing Ta2O5. The well known charge trapping in pre-existing traps operates only at low level stress resulting in small SILC at accumulation. The new trap generation plays a key role in the SILC degradation and is the dominant mechanism controlling the SILC in lightly Al-doped Ta2O5 layers.  相似文献   

5.
Response of 8 nm Ta2O5 stacks with Al and Au gate electrodes to voltage stress at room temperature and at 100 °C is investigated. Stress-induced leakage current (SILC) reveals significant gate dependence and distinct difference to SILC in SiO2. The mechanisms for SILC generation and stress degradation are discussed. Unlike SiO2, pre-existing traps and positive charge build-up are recognized as a key factor for generation of SILC in Ta2O5 stacks.  相似文献   

6.
Lightly Al-doped Ta2O5 films (10;15 nm) obtained by rf sputtering have been studied with respect to their dielectric and electrical properties. The formed metal-high-k dielectric-semiconductor capacitors have been characterized by capacitance-voltage and temperature-dependent current-voltage characteristics. It was established that the introduction of small amount (5 at.%) Al into the matrix of Ta2O5 improves dielectric constant, introduces negative oxide charge, suppresses deep oxygen-vacancy centers in Ta2O5 but creates shallow traps and changes the dominant conduction mechanism in the stacks. The doping produces more leaky films at room temperature and lower current at high temperature as compared to the case of pure Ta2O5. It is concluded that the strong contribution of tunneling processes through shallow traps in the conductivity of doped films could explain the observed current degradation at room temperature and its improved temperature stability at high temperatures. The energy levels of the traps responsible for the current transport are estimated.  相似文献   

7.
Electrical properties of mixed HfO2-Ta2O5 films (10;15 nm) deposited by rf sputtering on Si have been studied from the view point of their applications as high-k layers, by standard capacitance-voltage and temperature dependent current-voltage characteristics. The effect of HfO2 addition to the Ta2O5 is thickness dependent and the thicker layers exhibit advantages over the pure Ta2O5 (higher dielectric constant, enhanced charge storage density and improved interface quality). The process of HfO2 and Ta2O5 mixing introduces negative oxide charge, tends to creates shallow bulk traps and modifies the dominant conduction mechanisms in the stack capacitors as compared to the Ta2O5-based one (a contribution of tunneling processes through traps located below the conduction band of mixed layers to the leakage current in the HfO2-Ta2O5 stacks is observed). The traps involved in both Poole-Frenkel and tunneling processes are identified.  相似文献   

8.
The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of thermal thin film (15-35 nm) Ta2O5 capacitors has been investigated. The absolute level of leakage currents, breakdown fields, mechanism of conductivity, dielectric constant values are discussed in the terms of possible reactions between Ta2O5 and electrode material as well as electrode deposition process-induced defects acting as electrically active centers. The dielectric constant values are in the range 12-26 in dependence on both Ta2O5 thickness and gate material. The results show that during deposition of TiN and Al a reaction that worsens the properties of Ta2O5 occurs while there is not an indication for detectable reduction of Ta2O5 when top electrode is W, and the leakage current is 5-7 orders of magnitude lower as compared to Al and TiN-electroded capacitors. The high level of leakage current for TiN and Al gate capacitors are related to the radiation defects generated in Ta2O5 during sputtering of TiN, and damaged interface at the electrode due to a reaction between Al and Ta2O5, respectively. It is demonstrated that the quality of the top electrode affects the electrical characteristics of the capacitors and the sputtered W is found to be the best. The sputtered W gate provides Ta2O5 capacitors with a good quality: the current density <7 × 10−10 A/cm2 at 1 V (0.7 MV/cm, 15 nm thick Ta2O5). W deposition is not accompanied by an introduction of a detectable damage leading to a change of the properties of the initial as-grown Ta2O5 as in the case of TiN electrode. Damage introduced during TiN sputtering is responsible for current deterioration (high leakage current) and poor breakdown characteristics. It is concluded that the sputtered W top electrode is a good candidate as a top electrode of storage capacitors in dynamic random access memories giving a stable contact with Ta2O5, but sputtering technique is less suitable (favorable) for deposition of TiN as a metal electrode due to the introduction of radiation defects causing both deterioration of leakage current and poor breakdown characteristics.  相似文献   

9.
We compare charge carrier generation/trapping related degradation in control oxide (SiO2) and HfO2/SiO2 stack of an identical equivalent-oxide-thickness (EOT) during constant gate voltage stress of n-type metal-oxide-semiconductor (nMOS) capacitors. Irrespective of these two dielectrics, the kinetics of generation of both surface states and oxide-trapped positive charges are found to be similar. Our analysis shows that the positive oxide charge buildup during CVS is due to trapping of protons by the strained SiOSi bonds in either of the devices. We demonstrate that compared to SiO2 devices, HfO2 devices with an equal EOT better perform in CMOS logic applications. On the other hand, our results indicate that the control oxide is better in charge trapping memory devices. Furthermore, the lifetime of the control oxide devices is observed longer than that of HfO2 devices at a given operating voltage.  相似文献   

10.
In this paper, we present our results on the distribution and generation of traps in a SiO2/Al2O3 transistor. The investigation has been carried out by using charge pumping measurements, both variable voltage and frequency techniques, and constant voltage stress.By increasing the amplitude of the gate pulse we observe an increase of the charge recombined per cycle closely related to the contribution of shallow traps near the SiO2/Al2O3 interface. By reducing the pulse frequency we measure an increase in the charge pumping current due to traps located deeper in the Al2O3. By combining charge pumping and constant voltage stress measurements, we found that the traps are mostly generated near the Si/SiO2 interface.  相似文献   

11.
The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of Ta2O5 stack capacitors has been investigated. The leakage currents, breakdown fields, mechanism of conductivity and dielectric constant are discussed in the terms of possible reactions between Ta2O5 and electrode material as well as electrode-deposition-process-induced defects acting as electrically active centers. During deposition of TiN and Al a reaction that worsens the properties of Ta2O5 occurs while there is not an indication for detectable reduction of Ta2O5 when top electrode is W. The sputtered W top electrode is a good candidate as a gate of storage capacitors in DRAMs, but sputtering technique is less suitable for deposition of TiN due to the introduction of radiation defects causing deterioration of leakage current. Although some reaction between Al and Ta2O5 occurs, the resulting electrical properties of the capacitors are still acceptable.  相似文献   

12.
Tantalum pentoxide (Ta2O5) deposited by pulsed DC magnetron sputtering technique as the gate dielectric for 4H-SiC based metal-insulator-semiconductor (MIS) structure has been investigated. A rectifying current-voltage characteristic was observed, with the injection of current occurred when a positive DC bias was applied to the gate electrode with respect to the n type 4H-SiC substrate. This undesirable behavior is attributed to the relatively small band gap of Ta2O5 of around 4.3 eV, resulting in a small band offset between the 4H-SiC and Ta2O5. To overcome this problem, a thin thermal silicon oxide layer was introduced between Ta2O5 and 4H-SiC. This has substantially reduced the leakage current through the MIS structure. Further improvement was obtained by annealing the Ta2O5 at 900 °C in oxygen. The annealing has also reduced the effective charge in the dielectric film, as deduced from high frequency C-V measurements of the Ta2O5/SiO2/4H-SiC capacitors.  相似文献   

13.
Charge trapping and trap generation in field-effect transistors with SiO2/HfO2/HfSiO gate stack and TaN metal gate electrode are investigated under uniform and non-uniform charge injection along the channel. Compared to constant voltage stress (CVS), hot carrier stress (HCS) exhibits more severe degradation in transconductance and subthreshold swing. By applying a detrapping bias, it is demonstrated that charge trapping induced degradation is reversible during CVS, while the damage is permanent for hot carrier injection case.  相似文献   

14.
The trapping/detrapping behavior of charge carriers in ultrathin SiO2/TiO2 stacked gate dielectric during constant current (CCS) and voltage stressing (CVS) has been investigated. Titanium tetrakis iso-propoxides (TTIP) was used as the organometallic source for the deposition of ultra-thin TiO2 films at low temperature (<200 °C) on strained-Si/relaxed-Si0.8Ge0.2 heterolayers by plasma-enhanced chemical vapor deposition (PECVD) in a microwave (700 W, 2.45 GHz) plasma cavity discharge system at a pressure of 66.67 Pa. Stress-induced leakage current (SILC) through SiO2/TiO2 stacked gate dielectric is modeled by taking into account the inelastic trap-assisted tunneling (ITAT) mechanism via traps located below the conduction band of TiO2 layer. The increase in the gate current density observed during CVS from room temperature up to 125 oC has been analyzed and modeled considering both the buildup of charges in the layer as well as the SILC contribution. Trap generation rate and trap cross-section are extracted. A capture cross-section in the range of 10−19 cm2 as compared to 10−16 cm2 in SiO2 has been observed. A temperature-dependent trap generation rate and defects have also been investigated using time-dependent current density variation during CVS. The time dependence of defect density variation is calculated within the dispersive transport model, assuming that these defects are produced during random hopping transport of positively charge species in the insulating high-k stacked layers. SILC generation kinetics, i.e. defect generation probability under different injected fluences for various high-constant stress voltages in both polarities have been studied. An empirical relation between trap generation probability and applied stress voltage for various injected fluences has been developed.  相似文献   

15.
Although programming and erase speeds of charge trapping (CT) flash memory device are improved by using Al2O3 as blocking layer, its retention characteristic is still a main issue. CT flash memory device with Al2O3/high-k stacked blocking layer is proposed in this work to enhance data retention. Moreover, programming and erase speeds are slightly improved. In addition, sealing layer (SL), which is formed by an advanced clustered horizontal furnace between charge trapping layer and Al2O3 as one of the blocking layers is also studied. The retention characteristic is enhanced by SL approach due to lower gate leakage current with less defect. With the combination of SL and Al2O3/high-k stacked blocking layer approaches, retention property can be further improved.  相似文献   

16.
《Microelectronic Engineering》2007,84(9-10):1964-1967
We have investigated electrical stress-induced charge carrier generation/trapping in a 4.2 nm thick (physical thickness Tphy) hafnium oxide (HfO2)/silicon dioxide (SiO2) dielectric stack in metal-oxide-semiconductor (MOS) capacitor structures with negative bias on the gate. It is found that electron trapping is suppressed in our devices having an equivalent oxide thickness (EOT) as low as 2.4 nm. Our measurement results indicate that proton-induced defect generation is the dominant mechanism of generation of bulk, border and interface traps during stress. In addition, we have shown that constant voltage stress (CVS) degrades the dielectric quality more than constant current stress (CCS).  相似文献   

17.
A new charge trapping dynamics is proposed to analyze theoretically the gate oxide degradation in metal oxide silicon structures under Fowler–Nordheim (F–N) stress (6–10 MV/cm) at a low injected electron fluence. Devices studied were MOS capacitors with 22-, 27-, and 33-nm-thick, thermally grown silicon dioxide (SiO2) on (100) n-Si. Our model includes tunneling electron initiated band-to-band impact ionization and trap-to-band ionization, as the possible mechanisms for the generation of hole and positive charge in the bulk of the oxide, respectively. The results from our model are in good agreement with the experimental results of gate voltage shift with injected electron fluence under constant current stress. Based on the developed coupled dynamics, we have compared the degradation under F–N stress at a constant current and gate voltage.  相似文献   

18.
The behaviour of carrier mobility in the inversion channel of gateless p-MOSFETs with thin (7-50 nm) Ta2O5 layers, having a dielectric constant of (23-27) and prepared by rf sputtering of Ta in an Ar-O2 mixture, has been investigated. It is shown that independently of the high dielectric constant of the layers, the transport properties in the channel are strongly affected by defects in Ta2O5/Si system in the form of oxide charge and interface states. These defects act as scattering centers and are responsible for the observed minority carrier mobility degradation. Both, the oxide and the interface state charges are virtually independent on the oxygen content (in the range 10-30%) during the sputtering process. A reduction of the oxide charge and the density of interface states with increasing Ta2O5 film thickness was found, which results in the observed increase of the inversion channel mobility with thickness. It is assumed that the bond defects (broken or strained Ta-bonds as well as weak Si-O bonds in the transition region between Ta2O5 and Si) are much more probable sources of defect centers rather than Ta and O vacancies or impurities.  相似文献   

19.
In this paper, n++-poly/SiOx/SiO2/p-sub capacitors with enhanced electron injection under substrate accumulation are extensively studied. First, systematic investigation of the role of technology parameters in the PECVD deposition of the SiOx films is presented. In particular, the effect of the silane dilution parameter on the device performance is investigated and the SiOx film optimized in terms of reliability and electron injection enhancement. Then, investigation of the electrical behavior of n++ -poly/SiOx/SiO2/p-sub MOS capacitors is presented. As a result, a picture of the space defect distribution in the SiOx films is proposed. In SiOx films, a relevant density of trapped charge adds to ionized impurities. In particular, the net charge is negative in the bulk of the dielectric, indicating that trapped electrons exceed all the other charge contributions. The space distribution of defects is strongly nonuniform and has the maximum in the vicinity of the SiOx/SiO2 interface. After dc current stress, the devices undergo electrical degradation, the dominant mechanism of degradation being the creation of interface hole traps. The trap generation model is based on the release of hydrogen and pairs generation in the SiOx films. The time-scale of trap filling during the stress is tens of seconds, which suggests that the stress-induced traps are deep in the energy gap  相似文献   

20.
Thin (10 nm) gate oxide MOS capacitors have been subjected to static and dynamic stress conditions. The evolution of the trapped charge distributions (characterized by average density and centroid) has been measured as a function of the stress time. The evolution of the average charge density for DC stresses shows that both polarities have identical trap generation rates and a constant average density of traps at breakdown. However, the final density of traps is much smaller for injection from the gate, so that the time-to-breakdown is also much shorter for this stress polarity. The evolution of the centroid shows that traps are always mainly generated near the cathodic interface. Unipolar dynamic stresses give results which are qualitatively very similar to those obtained under DC conditions and without a relevant frequency dependence. In contrast, bipolar stress experiments show significant qualitative differences, the frequency dependence being very important. In general, the trap generation and trapping rates are reduced in comparison to the DC and unipolar cases, this reduction being more important at high frequencies. In addition, the average density of trapped electrons at the breakdown is larger than that obtained in DC experiments. Both observations explain the tremendous increase in the mean-time-to-breakdown obtained under high-frequency stress conditions. The presented results are qualitatively explained in terms of microscopic degradation models  相似文献   

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