A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

A quad CMOS single-supply op amp with rail-to-rail output swing

The realization of a commercially viable, general-purpose quad CMOS amplifier is presented, along with discussions of the tradeoffs involved in such a design. The amplifier features an output swing that extends to either supply rail, together with an input common-mode range that includes ground. The device is especially well suited for single-supply operation and is fully specified for operation from 5 to 15 V over a temperature range of -55 to +125/spl deg/C. In the areas of input offset voltage, offset voltage drift, input noise voltage, voltage gain, and load driving capability, this implementation offers performance that equals or exceeds that of popular general-purpose quads or bipolar of Bi-FET construction. On a 5-V supply the typical V/SUB os/ is 1 Mv, V/SUB os/ drift is 1.3 /spl mu/V//spl deg/C, 1-kHz noise is 36 nV//spl radic/Hz, and gain is one million into a 600-/spl Omega/ load. This device achieves its performance through circuit design and layout techniques as opposed to special analog CMOS processing, thus lending itself to use on system chips built with digital CMOS technology.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

A CMOS chopper amplifier

A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.     

An NMOS comparator for a bubble memory

A low-noise low-offset comparator was designed for a bubble memory system. The measured noise performance was 25 /spl mu/V rms or 13 nV//spl radic/Hz and the worst case offset voltage was determined to be 158 /spl mu/V. This results in a 1.30 mV comparator gray region.     

A low-noise low-offset capacitive sensing amplifier for a 50-/spl mu/g//spl radic/Hz monolithic CMOS MEMS accelerometer

This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.     

Design of a low-noise preamplifier for nerve cuff electrode recording

This paper discusses certain important issues involved in the design of a nerve signal preamplifier for implantable neuroprostheses. Since the electroneurogram signal measured from cuff electrodes is typically on the order of 1 /spl mu/V, a very low-noise interface is essential. We present the argument for the use of BiCMOS technology in this application and then describe the design and evaluation of a complete preamplifier fabricated in a 0.8-/spl mu/m double-metal double-poly process. The preamplifier has a nominal voltage gain of 100, a bandwidth of 15 kHz, and a measured equivalent input-referred noise voltage spectral density of 3.3 nV//spl radic/Hz at 1 kHz. The total input-referred rms noise voltage in a bandwidth 1 Hz-10 kHz is 290 nV, the power consumption is 1.3 mW from /spl plusmn/2.5-V power supplies, and the active area is 0.3 mm/sup 2/.     

A low drift fully integrated MOSFET operational amplifier

A fully integrated MOSFET amplifier with very low drift has been built using standard technology. Input offset voltages as low as 5 /spl mu/V and drift values of this offset voltage less than 0.05 /spl mu/V//spl deg/C are measured.     

Design considerations for linear optically coupled isolation amplifiers

A hybrid optically coupled isolation amplifier is described which optimizes DC performance, bandwidth, physical size, and cost. The design utilizes a blend of monolithic and hybrid technologies to achieve this unique set of characteristics. The development of the linear optical coupler is traced. Optical and electronic circuit techniques are presented that combine, for the first time, precision performance with miniature packaging. Optional connections allow unipolar/bipolar and inverting/noninverting operation with both voltage and current inputs. Typical performance, based upon production runs, includes: 1000 V isolation voltage, 10 nA offset current, 1 pA//spl deg/C offset drift, 0.3 /spl mu/A barrier leakage at 60 Hz, 0.05 percent nonlinearity, and a bandwidth of over 60 kHz.     

Noise analysis and characterization of a sigma-delta capacitive microaccelerometer

This paper reports a high-sensitivity low-noise capacitive accelerometer system with one micro-g//spl radic/Hz resolution. The accelerometer and interface electronics together operate as a second-order electromechanical sigma-delta modulator. A detailed noise analysis of electromechanical sigma-delta capacitive accelerometers with a final goal of achieving sub-/spl mu/g resolution is also presented. The analysis and test results have shown that amplifier thermal and sensor charging reference voltage noises are dominant in open-loop mode of operation. For closed-loop mode of operation, mass-residual motion is the dominant noise source at low sampling frequencies. By increasing the sampling frequency, both open-loop and closed-loop overall noise can be reduced significantly. The interface circuit has more than 120 dB dynamic range and can resolve better than 10 aF. The complete module operates from a single 5-V supply and has a measured sensitivity of 960 mV/g with a noise floor of 1.08 /spl mu/g//spl radic/Hz in open-loop. This system can resolve better than 10 /spl mu/g//spl radic/Hz in closed-loop.     

Robust highly linear high-frequency CMOS OTA with IM3 below - 70 dB at 26 MHz

An enhanced configuration for a linearized MOS operational transconductance amplifier (OTA) is proposed. The proposed fully differential OTA circuit is based on resistive source degeneration and an improved adaptive biasing technique. It is robust to process variation, which has not been fully shown in previously reported linearization techniques. Detailed harmonic distortion analysis demonstrating the robustness of the proposed OTA is introduced. The transconductance gain is tunable from 160 to 340 /spl mu/S with a third-order intermodulation (IM3) below -70 dB at 26 MHz. As an application, a 26-MHz second-order low-pass filter fabricated in TSMC 0.35-/spl mu/m CMOS technology with a power supply of 3.3 V is presented. The measured IM3 with an input voltage of 1.4 Vpp is below - 65 dB for the entire filter pass-band, and the input referred noise density is 156nV//spl radic/Hz. The cutoff frequency of the filter is tunable in the range of 13-26 MHz. Theoretical and experimental results are in good agreement.     

MOS transistors operated in the lateral bipolar mode and their application in CMOS technology

Operation of an MOS transistor as a lateral bipolar is described and analyzed qualitatively. It yields a good bipolar transistor that is fully compatible with any bulk CMOS technology. Experimental results show that high /spl beta/-gain can be achieved and that matching and 1/f noise properties are much better than in MOS operation. Examples of experimental circuits in CMOS technology illustrate the major advantages that this device offers. A multiple current mirror achieves higher accuracy, especially at low currents. An operational transconductance amplifier has an equivalent input noise density below 0.1 /spl mu/V//spl radic/Hz for frequencies as low as 1 Hz and a total current of 10 /spl mu/A. A bandgap reference yields a voltage stable within 3 mV from -40 to +80/spl deg/C after digital adjustment at ambient temperature. Other possible applications are suggested.     

A compact 43-GHz monolithic differential VCO in 0.5-/spl mu/m InP DHBT technology

A compact monolithic integrated differential voltage controlled oscillator (VCO) using 0.5-/spl mu/m emitter width InP/InGaAs double-heterostructure bipolar transistors with a total chip size of 0.42 mm /spl times/ 0.46 mm is realized by using cross-coupled configuration for extremely high frequency satellite communications system applications. The device performance of F/sub max/ greater than 320 GHz at a current density of 5 mA//spl mu/m/sup 2/ and 5-V BVceo allows us to achieve a low phase noise 42.5-GHz fundamental VCO with -0.67-dBm output power. The VCO exhibits the phase noise of -106.8 dBc/Hz at 1-MHz offset and -122.3 dBc/Hz at 10-MHz offset from the carrier frequency.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

Micropower high-performance SC building block for integrated low-level signal processing

A switched-capacitor instrumentation amplifier which uses correlated-double sampling to reduce the amplifier offset is discussed. Additional offset caused by clock-related charge injection is cancelled by a symmetrical differential circuit topology and a three-phase clocking scheme. An experimental low-power test cell has been integrated, showing 100 /spl mu/V equivalent offset voltage and input noise equal to 270 /spl mu/V. For a fixed gain equal to 10- and 9-kHz sampling frequency, the power dissipation is 36 /spl mu/W (power supply: 5 V); the circuit measures only 0.2 mm/SUP 2/.     

Cryogenic capacitive transimpedance amplifier for astronomical infrared detectors

We have developed a new capacitive transimpedance amplifier (CTIA) that can be operated at 2 K, and have good performance as readout circuits of astronomical far-infrared array detectors. The circuit design of the present CTIA consists of silicon p-MOSFETs and other passive elements. The process is a standard Bi-CMOS process with 0.5 /spl mu/m design rule. The open-loop gain of the CTIA is more than 300, resulting in good integration performance. The output voltage swing of the CTIA was 270 mV. The power consumption for each CTIA is less than 10 /spl mu/W. The noise at the output showed a 1/f noise spectrum of 4 /spl mu/V//spl radic/Hz at 1 Hz. The performance of this CTIA nearly fulfills the requirements for the far-infrared array detectors onboard ASTRO-F, Japanese infrared astronomical satellite to be launched in 2005.     

New techniques for drift compensation in integrated differential amplifiers

A technique is described for achieving low-voltage offset and thermal drift in a monolithic integrated differential amplifier. First order compensation is achieved, under severe restrictions, for a simple differential pair. An alternative balancing technique utilizes the linear combination of two equal and opposite drift characteristics to minimize drift from all sources. Drift values of /spl plusmn/0.12 /spl mu/V//spl deg/C over the temperature range 0 to 100/spl deg/C have been obtained.     

A low input capacitance voltage follower in a compatible silicon-gate MOS-bipolar technology

Using a compatible silicon-gate p-MOS-bipolar technology (SIGBIP), a voltage follower is described with protected MOSFET input stage featuring less than 1-pA input current, less than 0.1-pF input capacitance, 10-MHz bandwidth, 20-/spl mu/V p-t-p noise from 1 Hz to 100 kHz. Offset drift is less than 30 /spl mu/V//spl deg/C. The circuit is based on a new very high-gain differential stage which allows full bootstrapping of all its input capacitances. The circuit measures only 0.9 mm/SUP 2/ and is mounted in a 4-pin TO-18 package. The circuit can successfully be used for charge measurements, and especially for wide-band measurements from very high impedance sources (>10 M/spl Omega/) as occurring in bioelectronics, biochemistry, etc.     

Internally matched, ultralow DC power consumption CMOS amplifier for L-band personal communications

An internally matched, extremely low operation voltage amplifier monolithic microwave integrated circuit (MMIC) has been implemented in a 0.35-/spl mu/m silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology for L-band personal communications. At 1.6 GHz the MMIC amplifier has a gain of 6.4 dB and a noise figure of 4.8 dB at a drain voltage of 0.6 V and a current of 2 mA. The MMIC amplifier exhibits a Gain/Power quotient as high as 5.33 dB/mW, which we believe is the highest recorded for Si CMOS MMIC technology.