Dual material gate silicon on insulator junctionless MOSFET for low power mixed signal circuits

In this research paper, demonstrates, the logic performance of n and p channel complementary metal oxide semiconductor (CMOS) circuits implemented with dual material gate silicon on insulator junctionless transistor (DMG SOI JLT). The logic performance of a CMOS circuit is evaluated in terms of static power dissipation, voltage transfer characteristic, propagation delay and noise margin. The gate capacitance is less as compared to gate capacitance of DMG SOI transistor in saturation. The power dissipation for CMOS inverter of DMG SOI JLT is improved by 25% as compared to DMG SOI transistor. The DMG SOI JLT common source amplifier has 1.25 times amplification as that of DMG SOI transistor. The noise margin of DMG SOI JLT CMOS inverter is improved by 23% as compared to the DMG SOI transistor CMOS inverter. The NAND gate static power dissipation of DMG SOI JLT is found improved imperically as compared to DMG SOI transistor for various channel length. The improvement obtained is 53% for 20nm, 46% for 30nm and 34% for 40nm respectively. Static power dissipation of DMG SOI JLT inverter is reduced by 3% as compared to junction transistor inverter at channel length of 30nm.     

Predicting CMOS speed with gate oxide and voltage scaling andinterconnect loading effects

Sub-quarter micron MOSFET's and ring oscillators with 2.5-6 nm physical gate oxide thicknesses have been studied at supply voltages of 1.5-3.3 V. I_dsat can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance. Gate delay and the optimal gate oxide thickness were modeled and predicted. Optimal gate oxide thicknesses for different interconnect loading are highlighted     

The investigation of key technologies for sub-0.1-μm CMOS devicefabrication

The fabrication of sub-0.1-μm CMOS devices and ring oscillator circuits has been successfully explored. The key technologies include: lateral local super-steep-retrograde (SSR) channel doping with heavy ion implantation, 40-nm ultrashallow source/drain (S/D) extension, 3-nm nitrided gate oxide, dual p⁺/n⁺ poly-Si gate electrode, double sidewall scheme, e-beam lithography and RIE etching for sub-0.1-μm poly-Si gate pattern, thin and low sheet resistance SALICIDE process, etc. By these innovations in the technologies, high-performance sub-0.1-μm CMOS devices with excellent short-channel effects (SCEs) and good driving ability have been fabricated successfully; the shortest channel length is 70 nm. 57 stage unloaded 0.1-μm CMOS ring oscillator circuits exhibiting delay 23.8 ps/stage at 1.5 V, and 17.5 ps/stage and 12.5 ps/stage at 2 V and 3 V, respectively, are achieved     

A standby current limited performance figure of merit for deepsub-micron CMOS

The delay time of an inverter or NAND chain at a gate length yielding equal standby current and active current is used as the definition of a maximum Figure of Merit (FOM), FOM_max. The circuit power that occurs under this condition of equal standby and active currents is an equally important measure. This FOM_max technique is particularly useful in characterizing complementary metal-oxide-semiconductor (CMOS) technologies in the deep submicron regime. A knowledge of the exact value of gate length is not necessary to apply the FOM_max methodology. For a fixed supply voltage and gate oxide thickness, node capacitance and transistor drive, and off currents determine the value of FOM_max. The value of gate length at which FOM_max occurs decreases with decreasing supply voltage. FOM_max analysis is applied to the comparison of CMOS technologies using gate oxide thicknesses of 5.7 and 3.8 nm     

Fabrication of submicrometer CMOS circuits using a new trilayer photolithographic process

CMOS circuits with submicrometer gate lengths were fabricated using a new trilayer photolithographic process. A transparent and electrically conductive film of indium tin oxide was used as the middle layer in the trilayer resist with unique advantages. The shortest on-mask gate length for which CMOS circuits were successfully fabricated was 0.75 µm. The corresponding effective channel lengths for NMOS and PMOS were on the order of 0.55 and 0.4 µm, respectively. A propagation delay of 106 ps at 5 V was achieved for CMOS ring oscillators fabricated using this process technology.     

Characterization of 1.9- and 1.4-nm ultrathin gate oxynitride by oxidation of nitrogen-implanted silicon substrate

For gate oxide thinned down to 1.9 and 1.4 nm, conventional methods of incorporating nitrogen (N) in the gate oxide might become insufficient in stopping boron penetration and obtaining lower tunneling leakage. In this paper, oxynitride gate dielectric grown by oxidation of N-implanted silicon substrate has been studied. The characteristics of ultrathin gate oxynitride with equivalent oxide thickness (EOT) of 1.9 and 1.4 nm grown by this method were analyzed with MOS capacitors under the accumulation conditions and compared with pure gate oxide and gate oxide nitrided by N/sub 2/O annealing. EOT of 1.9- and 1.4-nm oxynitride gate dielectrics grown by this method have strong boron penetration resistance, and reduce gate tunneling leakage current remarkably. High-performance 36-nm gate length CMOS devices and CMOS 32 frequency dividers embedded with 57-stage/201-stage CMOS ring oscillator, respectively, have been fabricated successfully, where the EOT of gate oxynitride grown by this method is 1.4 nm. At power supply voltage V/sub DD/ of 1.5 V drive current Ion of 802 /spl mu/A//spl mu/m for NMOS and -487 /spl mu/A//spl mu/m for PMOS are achieved at off-state leakage I/sub off/ of 3.5 nA//spl mu/m for NMOS and -3.0 nA//spl mu/m for PMOS.     

High Performance 70nm CMOS Devices

首次在国内成功地制作了栅长为70nm的高性能CMOS器件．为了抑制70nm器件的短沟道效应同时提高它的驱动能力,采用了一些新的关键工艺技术,包括3nm的氮化栅氧化介质,多晶硅双栅电极,采用重离子注入的超陡倒掺杂沟道剖面,锗预无定形注入加低能注入形成的超浅源漏延伸区,以及锗预无定形注入加特殊清洗处理制备薄的、低阻自对准硅化物等．CMOS器件的最短的栅长(即多晶硅栅条宽度)只有70nm,其NMOS的阈值电压、跨导和关态电流分别为0.28V、490mS/m和0.08nA／μm;而PMOS阈值电压、跨导和关态电流分别为－0.3V、340mS／mm和0.2nA／μm．并研制成功了100nm栅长的CMOS57级环形振荡器,其在1.5V、2V和3V电源电压下的延迟分别为23.5ps/级、17.5ps/级和12.5ps/级．     

A metal-gate self-aligned MOSFET using nitride oxide

A new method for making metal-gate self-aligned transistors using a thin nitrided oxide (12 nm) as a gate dielectric has been demonstrated. The nitrided thermal oxide acts as both a local oxidation mask and the final gate dielectric to produce a self-aligned thick oxide in the source-drain region. The thick oxide reduces the overlap capacitance down to that of a self-aligned polysilicon-gate device while allowing the use of a metal gate with a much lower resistivity than the more commonly used polycrystalline silicon. A high-frequency capacitance-voltage technique has been used to measure gate to source-drain overlap capacitance. The overlap capacitance was measured for a range of source-drain oxide thicknesses from 370 down to 255 nm. The capacitance increased from 0.64 to 0.74 fF/µm. The overlap capacitance of a self-aligned polycrystalline silicon-gate device with similar processing parameters was 0.98 fF/µm. The channel mobility has been determined to be approximately 350 cm²/V . s. Transistors with channel lengths as low as 0.7/µm were fabricated. Ring oscillators were also fabricated with stage-delays as low as 300 ps at 1.5 V and power-delay products of 70 fJ.     

On the SiO2-based gate-dielectric scaling limit forlow-standby power applications in the context of a 0.13 μm CMOS logictechnology

This paper describes a leading-edge 0.13 μm low-leakage CMOS logic technology. To achieve competitive off-state leakage current (I _off) and gate delay (T_d) performance at operating voltages (V_cc) of 1.5 V and 1.2 V, devices with 0.11 μm nominal gate length (L_g-nom) and various gate-oxide thicknesses (T_ox) were fabricated and studied. The results show that low power and memory applications are limited to oxides not thinner than 21.4 Å in order to keep acceptable off-state power consumption at V_cc=1.2 V. Specifically, two different device designs are introduced here. One design named LP (T_ox=26 Å) is targeted for V_cc=1.5 V with worst case I_off <10 pA/μm and nominal gate delay 24 ps/gate. Another design, named LP1 (T_ox=22 Å) is targeted for V_cc =1.2 V with worst case I_off<20 pA/μm and nominal gate delay 27 ps/gate. This work demonstrates n/pMOSFETs with excellent 520/210 and 390/160 μA/μm nominal drive currents at V_cc for LP and LP1, respectively. Process capability for low-power applications is demonstrated using a CMOS 6T-SRAM with 2.43 μm² cell size. In addition, intrinsic gate-oxide TDDB tests of LP1 (T _ox=22 Å) demonstrate that gate oxide reliability far exceeding 10 years is achieved for both n/pMOSFETs at T=125°C and V _cc=1.5 V     

高性能亚100nm栅长氮氧叠层栅介质难熔W/TiN金属栅电极CMOS器件

在国内首次将等效氧化层厚度为1.7nm的N/O叠层栅介质技术与W/TiN金属栅电极技术结合起来,用于栅长为亚100nm的金属栅CMOS器件的制备.为抑制短沟道效应并提高器件驱动能力,采用的关键技术主要包括:1.7nm N/O叠层栅介质,非CMP平坦化技术,T型难熔W/TiN金属叠层栅电极,新型重离子超陡倒掺杂沟道剖面技术以及双侧墙技术.成功地制备了具有良好的短沟道效应抑制能力和驱动能力的栅长为95nm的金属栅CMOS器件.在VDS=±1.5V,VGS=±1.8V下,nMOS和pMOS的饱和驱动电流分别为679和-327μA/μm.nMOS的亚阈值斜率,DIBL因子以及阈值电压分别为84.46mV/dec,34.76mV/V和0.26V.pMOS的亚阈值斜率,DIBL因子以及阈值电压分别为107.4mV/dec,54.46mV/V和0.27V.结果表明,这种结合技术可以完全消除B穿透现象和多晶硅耗尽效应,有效地降低栅隧穿漏电并提高器件可靠性.     

HMOS-CMOS-a low-power high-performance technology

HMOS-CMOS, a new high-performance bulk CMOS technology, is described. This technology builds on HMOS II, and features high resistivity p-substrate, diffused n-well and scaled n- and p-channel devices of 2-/spl mu/m channel length and 400-/spl Aring/ gate oxide thickness. The aggressive scaling of n and p devices results in 350-ps minimum gate delay and 0.04-pJ power delay product. HMOS-CMOS is a single poly technology suitable for microprocessor and static RAM applications. A 4K static RAM test vehicle is described featuring fully CMOS six-transistor memory cell, a chip size of 19600 mil/SUP 2/, 75 /spl mu/W standby power, data retention down to a V/SUB cc/ voltage of 1.5 V and a minimum chip select and address access time of 25 ns.     

Effects of ionizing radiation on SOI/CMOS Devices fabricated in zone-melting-recrystallized Si films on SiO2

The effects of ionizing radiation on SOI/CMOS devices fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates have been investigated as a function of the negative bias applied to the substrate during irradiation and measurement. For these devices, which have a thin gate oxide 10 nm thick, the optimum substrate bias is - 5 V. For total doses up to 10⁷rad(Si), with this bias they exhibit low subthreshold leakage currents (<0.2-pA/µm channel width), small threshold voltage shifts (<-0.18 V for n-channel devices and <-0.46 V for p-channel devices) and very little transconductance degradation (<5 percent).     

Impact of extrinsic and intrinsic parameter fluctuations on CMOScircuit performance

The yield of CMOS logic circuits satisfying a specific high performance requirement is demonstrated to be significantly influenced by the magnitude of critical-path delay deviations due to both extrinsic and intrinsic parameter fluctuations. To evaluate the impact of these parameter fluctuations, a static CMOS critical-path delay distribution is calculated from rigorously derived device and circuit models that enable projections for future technology generations. Two possible options are explored to attain a desired yield: (1) reduce performance by operating at a lower clock frequency; and (2) increase the supply voltage and, consequently, power dissipation, to satisfy the nominal critical-path delay. For the 50-nm technology generation, the delay and power dissipation increases are 12%-29% and 22%-6%, respectively, for extrinsic parameter standard deviations ranging from (a) 5% for effective channel length and 0% for gate oxide thickness and channel doping concentration to (b) 10% for effective channel length and 5% for gate oxide thickness and channel doping concentration. Combining both extrinsic and intrinsic fluctuations, the delay and power dissipation increase to 18%-32% and 31%-53%, respectively, thus demonstrating the significance of including the random dopant placement effect in future CMOS logic designs     

Multigigahertz CMOS dual-modulus prescaler IC

A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes simultaneously the characteristics of both the p-channel and n-channel transistors for low-power-supply-voltage operation. Two different gate oxide thicknesses of 175 and 100 Å have been used. The best prescalar fabricated with 175-Å gate oxide functions at 2.06 GHz with 25-m W power consumption (L_eff=0.5 μm; V_dd=3.5 V). Preliminary results for prescalars fabricated with 100-Å gate oxide show that 4.2-GHz operation is possible (L_eff=0.4 μm; V _dd=3.5 V). Power-supply voltage as low as 1.7 V can be used for the prescalar to function at 1 GHz with a power consumption of only 4 mW     

Optimization of embedded compact nonvolatile memories for sub-100-nm CMOS generations

The performance of compact nonvolatile memory cells, meant for embedded applications in advanced CMOS processes, is studied and analyzed in detail by means of technology computer-aided design (TCAD), and new experimental results are presented. Improvement of the memory performance is achieved. The key element of this improvement is access gate oxide thickness reduction combined with suitable design of the channel/source/drain doping profiles. An increase of the memory readout current by a factor of two was achieved with an excellent low-leakage current level of the access gate transistor. The increase of the read current allows faster read access, while the excellent subthreshold behavior of the access gate transistor allows aggressive scaling of the access gate length down to 160 nm. A gate voltage as low as 1 V can be used for reading the cell, so there is no need for voltage boosting. The source-side injection programming speed is increased by one order of magnitude for devices with thin access gate oxide. The compact cell is suited for embedded applications in sub-100-nm CMOS generations.     

Analysis of leakage currents and impact on off-state powerconsumption for CMOS technology in the 100-nm regime

Off-state leakage currents have been investigated for sub-100 nm CMOS technology. The two leakage mechanisms investigated in this work include conventional off-state leakage due to short channel effects and gate leakage through ultrathin gate oxides. The conventional off-state leakage due to short channel effects exhibited the similar characteristics as previously published; however, gate leakage introduces two significant consequences with respect to off-state power consumption: (1) an increase in the number of transistors contributing to the total off-state power consumption of the chip and (2) an increase in the conventional off-state current due to gate leakage near the drain region of the device. Using experimentally measured data, it is estimated that gate leakage does not exceed the off-state specifications of the National Technology Roadmap for Semiconductors for gate oxides as thin as 1.4 to 1.5 nm for high performance CMOS. Low power and memory applications may be limited to an oxide thickness of 1.8 to 2.0 nm in order to minimize the off-state power consumption and maintain an acceptable level of charge retention. The analysis in this work suggests that reliability will probably limit silicon oxide scaling for high performance applications whereas gate leakage will limit gate oxide scaling for low power and memory applications     

Technology design for high current and ESD robustness in a deepsubmicron CMOS process

The intrinsic ESD/EOS robustness of a technology is determined by the sensitivity to thermal initiated second breakdown. We show, for the first time, high current and ESD robustness results for a deep submicron CMOS technology with drawn poly gate lengths of 0.35 μm and oxide thicknesses down to 4.5 nm. It is shown that a transistor design window can be determined for optimized drive current and good robustness, while maintaining low off currents. An important observation is that robustness increases for smaller channel lengths and is directly proportional to the transistor drive current. Hence, robust deep submicron technologies can be designed with optimized transistor performance without using additional masks or increasing process complexity     

NBTI degradation effect on advanced-process 45 nm high-k PMOSFETs with geometric and process variations

Negative bias temperature instability (NBTI) has become an important reliability concern for nano-scaled complementary metal oxide (CMOS) devices. This paper presents the effect of NBTI for a 45 nm advanced-process high-k dielectric with metal gate PMOS transistor. The device had incorporated advanced-process flow steps such as stress engineering and laser annealing in order to achieve high on-state drain current drive performance. To explore NBTI effects on an advanced-process sub-micron device, the 45 nm high-k PMOS transistor was simulated extensively with a wide range of geometric and process variations. The device was simulated at varying thicknesses in the dielectric layer, oxide interfacial layer, metal gate and polysilicon layer. In order to observe the NBTI effect on process variation, the NBTI degradation of the 45 nm advanced-process PMOS is compared with a 45 nm PMOS device which does not employ process-induced stress and incorporates the conventional rapid thermal annealing (RTA) as compared to the laser annealing process which is integrated in the advanced-process device flow. The simulation results show increasing degradation trend in terms of the drain current and threshold voltage shift when the thicknesses of the dielectric layer, oxide layer as well as the metal gate are increased.     

MOSFET doping profiling

An automated technique was developed for rapid measurement of MOSFET channel doping profiles. The technique is based on the well-known relationship between the device threshold voltage and substrate bias. It uses only DC voltage measurements and is not subject to the limitations of conventional capacitance-voltage (C-V) methods. An operational amplifier feedback circuit is used to determine the threshold voltage automatically as the substrate bias voltage is varied. Doping profiles determined with this technique agree very well with those obtained from C-V and from spreading resistance measurements, as well as with those predicted by SUPREM-3. The devices were fabricated with processes representing two generations of CMOS technology. The doping concentrations, channel implants, and gate oxide thicknesses varied significantly between the two, allowing the assessment of the accuracy of doping profile extraction techniques for devices representing a wide performance range     

Active Layer Thickness Effects on the On-State Current and Pulse Measurement at Room Temperature on Deposited Zinc Oxide Thin-Film Transistors

This study reports on the fabrication of thin-film transistors (TFTs) with transparent zinc oxide (ZnO) semiconductors serving as the active channel and silicon dioxide (SiO₂) serving as the gate insulator. The ZnO films were deposited by radiofrequency magnetron sputtering at room temperature. Moreover, the effects of channel thickness on the structural and pulse current?Cvoltage characteristics of ZnO TFTs using a bottom gate configuration were investigated. As the channel thickness increased, the crystalline quality and the channel conductance were enhanced. The electrical characteristics of TFTs exhibited field-effect mobilities of 8.36?cm²/Vs to 16.40?cm²/Vs and on-to-off current ratios of 10⁸ to 10⁷ for ZnO layer thickness of 45?nm and 70?nm, respectively. The threshold voltage was in the range of 10?V to 31?V for ZnO layer thicknesses from 35?nm to 70?nm, respectively. The low deposition and processing temperatures make these TFTs suitable for fabrication on flexible substrates.