40 Gbit/s lumped-element modulator driver in GaAs pHEMTs

A high-speed and high-gain modulator driver circuit using 0.15 /spl mu/m gate length GaAs pHEMT technology is presented. The IC was developed for driving electroabsorption modulators in 40 Gbit/s optical fibre systems. To meet application requirements a lumped-element approach was used with differential configuration. Measured results show the circuit operates at 40 Gbit/s with a swing of 3 V/sub p-p/ for single-ended and 6 V/sub p-p/ for differential output, and 8/10 ps rise/fall times.     

Low power optical gate HBT driver array for 2.5 Gbit/s ATMswitching

A four element driver array for optical gates in a 2.5 Gbit/s optical ATM switch is presented. The circuit uses a GaAs-GaAlAs heterojunction bipolar transistor (HBT) technology. It enables a switching time of <300 ps and current up to 150 mA with <400 mW per gate power consumption     

High frequency divider circuits using ion-implanted GaAs MESFET's

A single clock master-slave frequency divider circuit was designed and fabricated using GaAs MESFET's in the direct-coupled FET logic (DCFL) circuit architecture. At room temperature, the maximum operating frequency was 6.2 GHz at a power consumption of 3.5 mW/gate. The complete divider circuit and buffer amplifier was realized in a 65 × 165 µm²area. The MESFET's were fabricated using Si ion implantion directly into GaAs wafers and used a self-aligned recessed gate. The nominal gatelength was 0.6 µm. Corresponding fabricated ring oscillator circuits showed minimum gate delays of 18.5 ps at 3.1 mW/gate for fan-out of one at 300 K and 15.2 ps at 3.5 mW/gate at 77 K.     

Diode multiplexer in the multi-Gbit/s range

A clocked multiplexer circuit was realised which provided 4.48 Gbit/s, 5 Gbit/s, and 7.84 Gbit/s output-pulse streams for p.c.m.-type input tributaries at 1.12 Gbit/s, 0.25 Gbit/s, and 1.12 Gbit/s, respectively. The circuit employed essentially ultra-broadband 180° hybrids, step-recovery diodes, and GaAs Schottky-barrier diodes. Output voltages up to 2 V were obtained across a load of 50 ?. The pulse width of the output pulses was approximately 100 ps.     

InP DHBT-Based Monolithically Integrated CDR/DEMUX IC Operating at 80 Gbit/s

In this paper, a monolithically integrated clock and data recovery (CDR) circuit with 1:2 demultiplexer (DEMUX), which is intended for use in 80 Gbit/s optical fiber links, is presented. The integrated circuit (IC) is manufactured using an in-house InP double heterostructure bipolar transistor (DHBT) technology, exhibiting cut-off frequency values of more than 220 GHz for both$f_T$and$f_max $. The CDR circuit in the topology of a phase-locked loop (PLL) is mainly composed of a half-rate linear phase detector including a 1:2 demultiplexer (DEMUX), a loop filter, and a voltage-controlled oscillator (VCO). Hence, the corresponding architecture of each of these components as well as the applied circuit design technique are extensively addressed. Concerning the performance achieved by the CDR/DEMUX IC, the recovered and demultiplexed 40 Gbit/s data from an 80 Gbit/s input signal feature clear eye opening with a signal swing as high as 600$hboxmV_ pp$. The extracted 40 GHz clock signal shows a phase noise as low as$- hbox98~dBc/hboxHz$at 100 kHz offset frequency. The corresponding rms jitter amounts to 0.37 ps while the peak-to-peak jitter is as low as 1.66 ps. At a single supply voltage of$-hbox4.8~V$, the power consumption of the full CDR/DEMUX IC amounts to 1.65 W. To the authors' best knowledge, this work demonstrates the first CDR circuit at the achieved data rate, regardless of all the competing semiconductor technologies.     

High-performance implanted base silicon bipolar technology for RFapplications

A 0.4 μm silicon bipolar technology for mixed digital/analog RF-applications is described. Without increasing the process complexity in comparison to current production technologies transit frequencies of 52 GHz, maximum oscillation frequencies of 65 GHz and minimum noise figures of 0.7 and 1.3 dB at 3 and 6 GHz are achieved. Emitter-coupled logic (ECL) ring oscillators have a minimum gate delay of 12 ps, the low power capability of the technology is proven by a current-mode logic (CML) power delay product of 5.2 fJ and a dynamic frequency divider operates up to 52 GHz. These results demonstrate the suitability of this technology for mobile communications up to at least 6 GHz and for high-speed optical data links at 10 Gbit/s and above     

Clock recovery for a 5 Gbit/s fibre-optic system

A clock recovery circuit has been constructed using dual-gate MESFETs. From a 5 Gbit/s data stream consisting of 50 time division multiplexed 100 MHz channels, the 100 MHz master clock is recovered both in frequency and in phase. Phase jitter is less than 20 ps in the presence of data and channel noise. A significant advantage of this approach over previous ones is the simplicity in the clock recovery circuitry and in demultiplexing individual channels. This permits easy speed upgrading to beyond 10 Gbit/s.     

High performance 10-12.5 Gbit/s modulator driver in InP SHBT technology

A high performance modulator driver circuit is presented using 4" InP SHBT technology. The IC was developed for driving EAM modulators in OC-192 (10 Gbit/s) and with forward error correction (FEC: 10.7 Gbit/s or 12.5 Gbit/s) optical fibre systems. The monolithic integrated circuit features output amplitude control, output crossing point control and output DC offset control. Measured results show the circuit operates at 10 to 12.5 Gbit/s with a swing of 3.1 V/sub p-p/ at each output and 20/18 ps rise/fall times. The power dissipation is 1.4 W with a standard power supply of -5.2 V.     

10 Gbit/s AND gate using dual-gate GaAs MESFET

Using a commercial dual-gate GaAs MESFET transistor mounted in a microstrip circuit, an AND gate has been built. With the 100 ps (FWHM) wide test pulses available, a speed of 10 Gbit/s NRZ and a pulse suppression of at least 14 dB was obtained.     

Applications of single and dual gate GaAs MESFETs for Gbit/s optical data transfer systems

Intrinsic large signal rise and fall times of less than 30 ps without charge storage demonstrate the potential of single and dual gate GaAs MESFETs for Gbit/s optical communication systems. The applications as signal regenerator, bit synchronizer, laser modulator, multiplexer, and demultiplexer are shown. Using only one dual gate GaAs MESFET clock and pulse shape regeneration as well as 1 Gbit/s laser modulation is performed. Bit synchronization is demonstrated up to 4 Gbit/s. 1 to 2 Gbit/s and 2 to 4 Gbit/s multiplexing as well as 2 to 1 Gbit/s demultiplexing with additional clock and pulse shape regeneration is shown using dual gate FETs. 2 to 4 Gbit/s multiplexing without clock regeneration is also accomplished using single gate GaAs MESFETs.     

High speed GaAs digital integrated circuit with clock frequency of 4.1 GHz

A maximum clock frequency of 4.1 GHz was obtained for a GaAs digital integrated circuit using deep recess normally-on GaAs MESFETs with 1.2 ?m long gate and interdigitated Schottky diodes. The Ti/Pt/Au gate electrode was made by a lift-off technique with conventional photolithography. The minimum propagation delay of a NAND/AND gate was estimated to be 100 ps/gate for a fan-out of 2 from the self-oscillation frequency of the master-slave flip-flops.     

一种新型的高速时钟数据恢复电路的设计和验证

针对高速(Gbit/s)串行数据通信应用,提出了一种混合结构的高速时钟数据恢复电路。该电路结构结合鉴频器和半速率二进制鉴相器,实现了频率锁定环路和相位恢复环路的同时工作。和传统的双环路结构相比,在功耗和面积可比拟的前提下,该结构系统的复杂度低、响应速度快。电路采用1.8 V,0.18μm CMOS工艺流片验证,测试结果显示在2 Gbit/s伪随机数序列输入情况下,电路能正确恢复出时钟和数据。芯片面积约0.5 mm~2,时钟数据恢复部分功耗为53.6 mW,输出驱动电路功耗约64.5 mW,恢复出的时钟抖动峰峰值为45 ps,均方根抖动为9.636 ps。     

An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

40 Gbit/s monolithic integrated modulator driver in InP SHBT technology

A high-speed and high-gain modulator driver circuit is presented using 4-inch InP SHBT technology. The IC was developed for driving EAM modulators in 40 Gbit/s optical fibre systems. The monolithic integrated circuit features output amplitude control and output crossing point control. Measured results show the circuit operates at 40 Gbit/s with a swing of 2.5 V/sub p-p/ at each output and 9/8 ps rise/fall times. The power dissipation is 1.5 W with a standard power supply of -5.2 V.     

High-speed frequency dividers with quasi-normally-off GaAs MESFETs

Master-slave binary frequency dividers have been designed and implemented with enhancement-mode GaAs MESFETs by using the so-called LPFL logic approach. A wide range of speed-power performances has been observed: a maximum toggle frequency of 2.8 GHz at P = 15 mW/gate on a dual-clocked frequency divider and an fc,max of 1.73 GHz at Pxtpd = 1 pJ/gate on a single-clocked one. The high-speed performance obtained corresponds to a propagation delay of 145 ps for the constituent NOR-OR gates of fan-in/fan-out = 4/3, and it is made possible by careful optimisation of circuit design parameters.     

2.488 Gbit/s时钟数据恢复电路的设计

利用Cadence集成电路设计软件,基于SMIC 0.18 μm 1P6M CMOS工艺,设计了一款2.488 Gbit/s三阶电荷泵锁相环型时钟数据恢复(CDR)电路.该CDR电路采用双环路结构实现,为了增加整个环路的捕获范围及减少锁定时间,在锁相环(PLL)的基础上增加了一个带参考时钟的辅助锁频环,由锁定检测环路实时监控频率误差实现双环路的切换.整个电路由鉴相器、鉴频鉴相器、电荷泵、环路滤波器和压控振荡器组成.后仿真结果表明,系统电源电压为1.8V,在2.488 Gbit/s速率的非归零(NRZ)码输入数据下,恢复数据的抖动峰值为14.6 ps,锁定时间为1.5μs,功耗为60 mW,核心版图面积为566 μm×448μm.     

Gate-length dependence of the speed of SSI circuits using submicrometer selectively doped heterostructure transistor technology

Frequency dividers and ring oscillators have been fabricated with submicrometer gates on selectively doped AIGaAs/GaAs heterostructure wafers. A divide-by-two frequency divider operated up to 9.15 GHz at room temperature, dissipating 25 mW for the whole circuit at a bias voltage of 1.6 V, with gate length ∼ 0.35 µm. A record propagation delay of 5.8 ps/gate was measured for a 0.35-µm gate 19- stage ring oscillator at 77 K, with a power of 1.76 mW/gate, and a bias voltage of 0.88 V. The maximum switching speed at room temperature was 10.2 ps/gate at 1.03 mW/gate and 0.8 V bias, for a ring oscillator with the same gate length. With a range of gate lengths on the same wafer fabricated by electron-beam lithography, a clear demonstration of gate-length dependence on the propagation delay was observed for both dividers and ring oscillators.     

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency f/sub T/ and maximum oscillation frequency f/sub max/ of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.     

A 6 K-gate GaAs gate array with a new large-noise-margin SLCF circuit

A 6 K-gate GaAs gate array has been successfully designed and fabricated using a novel large-noise-margin Schottky-diode level-shifter capacitor-coupled FET logic (SLCF) circuitry and a WN/SUB x/ gate selfaligned lightly doped drain (LDD) structure GaAs MESFET process. Chip size was 8.0/spl times/8.0 mm/SUP 2/. A basic cell can be programmed as an SLCF inverter, a two-input NOR, or a two-input NAND gate. The unloaded propagation delay time was 76 ps/gate a 1.2-mW/gate power dissipation. The increases in delay time due to various loading capacitances were 10 ps/fan-in, 45 ps/fan-out, and 0.64 ps/IF. A 16-b serial-to-parallel-to-serial (S/P/S) data-conversion circuit was constructed on the gate array as an application example. A maximum operation frequency of 852 MHz was achieved at a 952-mW power dissipation, including I/O buffers.     

An E-Beam Fabricated GaAs D-Type Flip-Flop IC

A first generation of monolithic digital IC's using normally-on type GaAs MESFET's with 1.2-mu m gate length was initially developed. This technology leads to logic gates with propagation delays in the range 130-170 ps. It was applied to the fabrication of an edge-triggered D-type flip-flop IC whose perfomance is presented: minimum data pulsewidth (350 ps), maximum toggle frequency (up to 1.6 GHz), data input sensitivity. An improved technology intended for higher speeds is now under development. It utilizes direct-writing E-beam lithography to delineate 0.75-mu m gate length devices with extremely high alignment accuracy. This fabrication process leads to 61 ps (4 pJ) or 68 ps (2 pJ) propagation delays measured on a dual-ring oscillator test circuit. Recent advances in N/N/sup -/ epitaxial deposition techniques make these performances very uniform and satisfactorily reproducible. D-type flip-flop IC's have been fabricated with this new technology using a reduced (-1 to -1.5 V) pinchoff voltage value. Stable D-type operation up to 3-GHz clocking frequencies has been experimentally observed with a corresponding speed-power product of 2.6 pJ/gate.