Static characteristics of a-Si:H dual-gate TFTs

This paper examines the effect of the top gate on the static characteristics of dual-gate hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs). Both forward and reverse regimes of operation are considered. The top gate has a distinct effect on the threshold voltage, subthreshold slope, drive-current capability, and the leakage current of the TFT. In particular, the threshold voltage is found to linearly decrease with increasing top-gate bias. Specific bias configurations of the dual gate TFT critical to vertical integration of on-pixel electronics for imaging and display applications are also presented.     

a—Si：H TFT电流—电压特性研究

本文发展了一种研究ａ－Ｓｉ：Ｈ ＴＦＴ电流－电压特性的新方法。基于局域态电荷密度解析统一模型，提出并深入分析了沟道区有效温度参数的概念，并由此推导出了ａ－Ｓｉ：Ｈ ＴＦＴ电流－电压特性的解析表达式。其理论值与实验值符合很好。该模型可用于ａ－Ｓｉ：Ｈ ＴＦＴ静态特性分析及其电路优化。     

Modeling of the reverse characteristics of a-Si:H TFTs

This paper investigates the reverse current-voltage (I-V) characteristics of inverted staggered hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs). Three mechanisms have been identified as the source of the reverse current: ohmic conduction, front channel conduction, and backchannel conduction. Ohmic conduction constitutes the physical limit for the reverse current and is due to the intrinsic conductivity of the a-Si:H and associated dielectric layers, which correlates with process integrity. The accumulation of holes and electrons at the front and back a-Si:H/a-SiN_x:H interfaces, respectively, forms the basis of the other two leakage mechanisms. The relative dominance of the one or the other mechanism depends on bias conditions, TFT geometry, and process conditions. This paper identifies these sources of leakage current and examines the effect of the critical geometrical parameters (such as channel length and overlap length) and bias conditions on these leakage components. Physical models to predict bias and geometry dependences are presented for a quantitative analysis of the leakage current. Modeling results corroborate experimental observations of leakage current extracted from a large number of TFTs that are put in parallel for improved measurement accuracy. The physical parameters of the model provide a method for estimation of the significant interface and bulk properties of the structure     

Back channel etch chemistry of advanced a-Si:H TFTs

We report on the effects of back channel etch depth and etchant chemistry on the electrical characteristics of inverted staggered advanced amorphous silicon thin-film transistors. We found that the optimum amorphous silicon film thickness in the channel is about 800-1100 Å. Three dry etch, HBr + Cl₂, C₂F₆, and CCl₂F₂ + O₂, and one wet etch, KOH, chemistries are used for the back channel etch processing. We established that dry etch can be used for the back channel etch of amorphous silicon transistor without degrading its electrical characteristics.     

A novel a-Si:H AMOLED pixel circuit based on short-term stress stability of a-Si:H TFTs

This letter presents a novel pixel circuit for hydrogenated amorphous silicon (a-Si:H) active matrix organic light-emitting diode displays employing the short-term stress stability characteristics of a-Si:H thin film transistors (TFTs). The pixel circuit uses a programming TFT that is under stress during the programming cycle and unstressed during the drive cycle. The threshold voltage shift (V/sub T/-shift) of the TFT under these conditions is negligible. The programming TFT in turn regulates the current of the drive TFT, and the pixel current therefore becomes independent of the threshold voltage of the drive TFT.     

Dynamic Response of Normal and Corbino a-Si:H TFTs for AM-OLEDs

The dynamic characteristics of normal and Corbino hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) have been investigated. Top- and bottom-gate normal a-Si:H TFTs and bottom-gate Corbino a-Si:H TFTs were fabricated with a five-photomask process used in the processing of the active-matrix liquid crystal displays. The charging time and feedthrough voltage $Delta V_{P}$ measurement indicates that the normal a-Si:H TFT shows a similar behavior regardless of its TFT geometrical structure. Using a simple gate-to-source capacitance $C_{rm GS}$ model, the dependence of $Delta V_{P}$ on gate-to-source overlap and storage capacitor has closely been estimated using analytical calculation. Due to a unique electrode geometry, the Corbino a-Si:H TFT shows a small deviation from an analytical model used for the normal a-Si:H TFT, and consequently, a modified analytical model was developed. We also developed concepts of its possible application as a switching device to active-matrix organic light-emitting displays.      

A novel current-scaling a-Si:H TFTs pixel electrode circuit for AM-OLEDs

Hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) pixel electrode circuit with a function of current scaling is proposed for active-matrix organic light-emitting displays (AM-OLEDs). In contrast to the conventional current mirror pixel electrode circuit, in this circuit a high data-to-organic light-emitting device (OLED) current ratio can be achieved, without increasing the a-Si:H TFT size, by using a cascade structure of storage capacitors. Moreover, the proposed circuit can compensate for the variations of TFT threshold voltage. Simulation results, based on a-Si:H TFT and OLED experimental data, showed that a data-to-OLED current ratio larger than 10 and a fast pixel programming time can be accomplished with the proposed circuit.     

Estimate Threshold Voltage Shift in a-Si:H TFTs Under Increasing Bias Stress

A method of estimating threshold voltage shift in hydrogenated amorphous silicon (a-Si:H) transistors under increasing bias stress is proposed. Although the threshold voltage shift in a-Si:H thin-film transistor (TFT) has been modeled well under constant bias stress, its property with increasing bias stress, which occurs in many a-Si:H-based compensating circuits, still cannot be quantified without any restriction, such as constant overdrive bias or short stressing time. In this paper, we propose a model which is effective under an arbitrary increasing stress for a prolonged time. The proposed model reduces to the constant bias model if the stress bias remains unchanged. With this method, the lifetime of most compensating circuits based on a-Si devices can be estimated completely.      

a-Si:H TFTs using low-temperature CVD of Si/sub 3/H/sub 8/

a-Si:H layers have been deposited by chemical vapour deposition (CVD) at 350 degrees C using Si/sub 3/H/sub 8/ as the source gas. Inverted staggered gate thin-film transistors (TFTs) were fabricated with plasma-CVD-grown SiN/sub x/ as the gate insulator. Electron field-effect mobilities of 0.45 cm/sup 2//Vs were obtained and the on/off ratio in the drain current was 10/sup 6/.<>     

Stability of nc-Si:H TFTs With Silicon Nitride Gate Dielectric

We report the fabrication and characterization of bottom-gate and top-gate nanocrystalline silicon (nc-Si:H) thin-film transistors (TFTs) with amorphous-silicon nitride (a-SiN_x:H) as the gate dielectric. The devices were fabricated using standard 13.56-MHz plasma-enhanced chemical vapor deposition at 240 degC. Here, the same 80-nm nc-Si:H channel, 300-nm a-SiN_x:H gate dielectric, and 60-nm n⁺ nc-Si:H ohmic contact layers were used in both TFT structures. We analyzed the effects of gate configuration on TFT performance and, in particular, the electrical stability. The stability tests were carried out at a gate bias stress in the range from 20 to 40 V. The nc-Si:H TFTs demonstrated much better threshold-voltage (V_T ) stability compared with the amorphous-silicon (a-Si:H) counterparts, offering great promise for applications in active-matrix organic light-emitting diode (AMOLED) displays     

Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail states

An analytical drain current model for a-Si:H TFTs obtained by considering deep and tail states simultaneously is presented. Using an effective temperature approach, the localised deep and tail states have been considered in the DC model such that no approximations are needed. As verified by the published data, this analytical DC model provides an accurate prediction of the drain current characteristics of an a-Si:H thin film transistor.<>     

Stability analysis of current programmed a-Si:H AMOLED pixel circuits

In this paper, we present self-compensating current mirror-based pixel circuits, and analyze basic stability issues to provide a deeper understanding of circuit operation, and the impact of thin film transistor bias nonidealities, which can lead to the long-term (and gradual) instabilities in pixel drive current. The analysis also provides the circuit designer a means to tailor the pixel drive current stability to the long-term brightness degradation characteristics of the organic light-emitting diode.     

用光热偏转谱拟合计算研究非晶硅缺陷态及其稳定性

通过光热偏转谱（ＰＤＳ）研究了衬底温度对用超高频辉光放电（ＶＨＦ－ＧＤ）制备的ａ－Ｓｉ：Ｈ光学特性的影响，考虑了电子在缺陷态的相关统计，数字拟合各样品在不同亚稳状态下ＰＤＳ次带吸收谱（０．８￣１．７ｅＶ），获得带尾态，光能隙，缺陷态分布及相关能等电子态结构参数。结果表明，缺陷态分布随光照时间向能隙深处移动，相关能增加，在电中性条件下，用迭代法求出费米能级与电导率，与实验结果吻合较好，分析讨论所用计     

C元素对N型a-Si:H薄膜微结构及电学特性的影响

采用等离子增强化学气相沉积(PECVD)工艺,制备了P-C二元复合掺杂氢化非晶硅(a-Si:H)薄膜,研究了C元素对N型a-Si:H薄膜暗电导率(σ)及电导激活能(Ea)的影响;利用激光拉曼光谱研究了C元素对薄膜微结构的影响,讨论了P-C二元复合掺杂a-Si:H薄膜电学性能与微结构之间的相互影响关系.结果表明:随着C掺杂量的增加,a-Si:H薄膜的短程有序度降低,中程有序度基本保持不变,缺陷逐渐减少;一定程度的C掺杂可使N型a-Si:H薄膜电导激活能降低而使薄膜的暗电导率升高,但过量的C掺杂使N型a-Si:H薄膜非晶网络结构有序度严重恶化,电导率出现明显下降趋势.

Abstract：

Hydrogenated amorphous silicon (a-Si:H) thin films doped with P and C were deposited by plasma enhanced chemical vapor deposition (PECVD).The influence of carbon on the dark conductivity,activation energy and mirostructure of the P-doped a-Si:H films was investigated by means of electrical measurment and Raman spectroscopy,and the relationship between electrical properties and microstructure of the films was also analyzed.It is shown from Raman spectra that the degree of short-range order and the defects of the films decreae with the increase of carbon doping,while the degree of intermediate-range order remains unchanged.A small amount of carbon can reduce the activation energy and enhance the dark conductivity of the P-doped a-Si : H thin films.However,excessive carbon makes the structural order of the amouphous network get worse which leads to a decline of dark conductivity.     

Surface treatment effect on the poly-Si TFTs fabricated by electric field enhanced crystallization of Ni/a-Si:H films

Self-aligned, p-channel polycrystalline silicon thin-film transistors (TFTs) were fabricated by electric field enhanced crystallization of a-Si:H in contact with the Ni catalyst, where a chemical solution of 97.5% H/sub 2/O:1% HF:1.5% H/sub 2/O/sub 2/ was used for a surface treatment on polycrystalline silicon films. The wet surface treatment was found to remarkably improve the electrical properties of TFTs, especially the leakage current and subthreshold slope. The enhanced performance was confirmed to be from the removal of the Ni impurity remaining as defect states at the surface and also from the ameliorated surface roughness of the polycrystalline silicon films.     

气体压强对磷掺杂a-Si:H薄膜电学性能的影响

用射频等离子增强化学气相沉积方法(RF-PECVD)制备磷掺杂氢化非晶硅(a-Si:H)薄膜,研究了辉光放电气体压强(20～80 Pa)对薄膜的暗电导率、电导激活能以及电阻温度系数的影响;利用激光喇曼光谱研究了气体压强对a-Si:H薄膜微结构的影响,并与薄膜的电学性能进行了综合讨论.结果表明:随着辉光放电气体压强的增加,a-Si:H薄膜的暗电导逐步减小,但电导激活能和电阻温度系数都有不同程度的增大;同时,薄膜内非晶网络的短程和中程有序程度逐渐恶化.     

Electrical and photoelectric properties of a-Si:H layered films: The influence of thermal annealing

The electrical and photoelectric properties of layered a-Si:H films obtained by cyclic plasmochemical deposition and the effect of thermal annealing on these properties have been studied. Unannealed films demonstrate high photosensitivity, with a photoconductivity to dark conductivity ratio of K=3.4×10⁶. Increasing the annealing temperature causes the film photosensitivity to fall because of a considerable decrease in the photoconductivity and increase in the dark conductivity. For films annealed at temperatures above 500°C, the conductivity is the sum of the band conductivity and the hopping conductivity via states at the Fermi level.     

Effect of Channel Width Shortening on the Stability of a-Si:H/nc-Si:H Bilayer Thin-Film Transistors

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V _on) and on-state current (I _on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V _on is observed, attributed to electron injection into the gate dielectric, followed by I _on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.     

准周期a-Si:H/a-SiN_x:H超晶格

本文首次报道成功地实现了非晶态半导体准周期(无平移对称性)超晶格结构.利用辉光放电汽相淀积技术,由两种超薄的a-Si:H层和a-SiN_x:H层按Fibonacci序列程序淀积而构成一维准周期超晶格.其中两种一维周期格子的调制波长比为黄金分割τ=(1+5~(1/2))/2.剖面电子显微像和相应的电子衍射花样揭示出这类新型非晶态半导体超晶格的奇异性质.简单的理论计算给予实验衍射图像以明确的物理解释.