Charge-transferred presensing, negatively precharged word-line, and temperature-insensitive power-up schemes for low-voltage DRAMs

A 256-Mb SDRAM is implemented with a 0.12-/spl mu/m technology to verify three circuit schemes suitable for low-voltage operation. First, a new charge-transferred presensing achieves fast stable low-voltage sensing performance without additional bias levels required in conventional charge-transferred presensing schemes. Second, a negative word-line scheme is proposed to bypass the majority of discharging current to VSS. Without switching signals, main discharging paths are automatically switched from VSS to VBB2 in response to the voltage of each discharging node itself. Finally, to initialize internal nodes during power-up, a temperature-insensitive power-up pulse generator is also proposed. The temperature coefficient of the setup voltage is adjustable through optimization of circuit parameters.     

应用于液体检测的级联长周期光纤光栅的温度减敏封装结构

研制了一种基于级联长周期光纤光栅对(LPFGP) 用作液体折射率检测的聚合物封装温 度减敏的新型结构。选用负热光系数的OE4110聚合物材料作为封装的 基底材料,封装结构中引入一个特殊的凹槽,方便 待测溶液通过通孔进入。封装后的LPFGP谐振波长温度灵敏度约10pm /℃,而相同参数的未封装的LPFGP的温度灵敏 度为120pm/℃,封装后的LPFGP大大降低了传感器谐振波长对温度变 化的灵敏度。本文的 封装装置融保护和温度补偿功能于一体,特殊的结构设计使之适用于液体折射率的检测。     

A flexible redundancy technique for high-density DRAMs

The limitations of conventional redundancy techniques are pointed out and a novel redundancy technique is proposed for high-density DRAMs using multidivided data-line structures. The proposed technique features a flexible relationship between spare lines and spare decoders, as well as lower probability of unsuccessful repair. With this technique the yield improvement factor of 64-Mb DRAMs and beyond is estimated to be more than twice that with the conventional technique in the early stages of production     

A temperature-insensitive erbium-doped fiber amplifier for terrestrial wavelength-division-multiplexing systems

We have evaluated a variation in the temperature dependence of an erbium-doped fiber gain spectrum by a pump wavelength in the 980-nm band for the first time. By optimizing both the pump wavelength in the 980-nm band and a temperature-sensitive gain flattening filter, the gain change of an erbium-doped fiber amplifier was successfully suppressed to 0.18 dB/sub pp/ in the temperature range between 0/spl deg/C and 65/spl deg/C and the wavelength range of 37.0 nm.     

A temperature-insensitive strain sensor using a fiber Bragg grating

A novel temperature-insensitive strain sensor based on a fiber Bragg grating is demonstrated. The front section of the fiber Bragg grating is fixed to a crystal plate, and the other section is linearly etched by HF acid. The reflected power and bandwidth of the grating vary linearly with strain and is insensitive to temperature variation.     

A built-in Hamming code ECC circuit for DRAMs

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique     

Optimized sensing scheme of DRAMs

The half-V_cc sensing scheme of CMOS dynamic RAMs (DRAMs) has been analyzed. It has been found that fluctuations of the cell-plate bias must be taken into account since they can degrade the sense signal. An improvement is possible by connecting the bit lines to the cell plate and its half-V_cc generator during precharge. Optimum performance of the sense amplifier is achieved if the PMOS and NMOS latches are activated simultaneously. The advantages are: (1) the sensitivity is improved due to the elimination of the offset contribution caused by unmatched capacitive loads; (2) the sensing speed is enhanced due to faster sense signal amplification; and (3) the peak current is reduced since the NMOS latch does not lower the voltage level of both bit line and reference bit line     

The state-of-the-art and future trends in DRAMs

The production of future generation DRAM devices critically requires R&D of process technologies for highly integrable and cost effective processes. Also, in order to support the ever-increasing requirements for high performance operation, the future DRAM products should be equipped with the capabilities of low voltage operation and high speed. This paper presents an overview of process technology for deep sub-micrometer devices such as a 256 Mbit DRAM based upon current research data and giga bit DRAMs.     

A new on-chip converter for submicrometer high-density DRAMs

The converter described is a feedback-type voltage regulator which supplies a reduced voltage to an entire RAM circuit. A novel timing activation method was introduced to save power. The converter has been implemented on an experimental 4-Mb dynamic RAM. It was found that an even faster access time and higher reliability compared to a conventional design could be achieved by using an on-chip voltage converter and shorter channel transistors. This voltage converter is suitable for high-density, high-speed, and high-reliability DRAMs with submicrometer transistors.     

一种温度不敏感频率范围宽的三角波振荡器

本文介绍了一种由双比较器型施密特触发器构成的三角波振荡器电路,它通过对电容恒流充放电产生对称三角波;此电路的优点是其产生的三角波的频率稳定且具有很高的精度,并对温度和电源的变化不敏感;文章最后给出了电路的Hspice仿真结果。     

光纤布拉格光栅温度不敏感振动传感器

介绍了一种新型的基于光纤布拉格光栅的温度不敏感的振动传感器.将光纤光栅倾抖粘贴在直角三角形悬臂梁的侧面,沿垂直方向的振动将导致悬臂梁沿长度方向的曲率周期性变化.悬肴梁弯曲使光纤布拉格光栅带宽展宽,其反射带宽和反射光强随着自由端挠度的变化而改变.在振动测量过程中,以传统的电阻应变片的测量结果作为此光纤光栅振动传感器的参照对比,两者所测得的振动频率相差小于0.5%.此外,由于光纤布拉格光栅的反射带宽和反射光强不随温度改变,所以此振动传感器具有温度不敏感性.     

温度不敏感型石英光滤波器的研究

为了解决石英光滤波输出随温度敏感的问题,利用温度的变化对石英双折射率和旋光率具有相反变化趋势的原理,提出了一种由石英双折射滤波器和石英旋光滤波器组合而成的新型温度不敏感型的滤波器,采用数值分析和实验研究的方法研究了温度对该新型石英滤波器透射中心波长的影响。结果表明,该新型石英滤波器在一定温度范围内是不灵敏的。这为石英滤波波长温度不敏感的应用提供了一种自适应温度补偿的方法。     

A novel temperature-insensitive strain sensor based on tapered fiber grating

A novel temperature-insensitive strain sensor based on bandwidth demodulation of the reflected light from the tapered fiber grating is presented, which is simple and low-cost and has considerable potential particularly application for strain sensing,and with the development of the interrogation system, it can demodulate both the bandwidth and the center wavelength of the reflected light from TFG to measure strain and temperature simultaneously.     

Accelerated hot electron effects in DRAMs

A number of 64K and 256K DRAMs were subjected to a voltage and temperature stress designed to accelerate hot electron effects. The access time and maximum retention time were examined for a variety of stress conditions. It was found that both hot electron trapping and interface state generation were probable causes of observed shifts in parameters. The change in maximum retention time was a more sensitive parameter than access time.     

A study of pipeline architectures for high-speed synchronous DRAMs

The performances of SDRAMs with different pipeline architectures are examined analytically on the basis of the time required to refill the on-chip cache of a Pentium CPU. The analysis shows that the cycle time of the conventional pipeline structures cannot be reduced because of its difficulty in distributing the access time evenly to each pipeline stage of the column address access path. On the contrary, the wave pipeline architecture can make the access path evenly divided and can increase the number of pipeline stages to achieve the shortest cache refill time. But the wave congestion at the output terminal of the wave pipeline path caused by access time fluctuation narrows the valid time window. The parallel registered wave pipeline architecture can remove the effect of access time fluctuation so that the cycle time is defined only by the data pulse width. If the data pulse width t_w<2 ns, even 500-MHz clock frequency can be obtained     

A dual-phase-controlled dynamic latched amplifier for high-speedand low-power DRAMs

A dual-phase-controlled dynamic latched (DDL) amplifier for a differential data transfer scheme designed to achieve both high speed and low power in DRAMs is described. This circuit reduces the excessive operating margin caused by device fluctuations by using a pair of dynamic latched amplifiers, controlled by a dual-phase clock, to automatically correct the output data. Two circuit technologies are used in the DDL amplifier to achieve 200-MHz operation in a 1-Gb SDRAM using 0.13-μm technology: a cycle-time-progressive control circuit that increases the operating frequency and a shared DDL amplifier technique that reduces the area penalty of the DDL amplifier. These techniques and circuits reduce the access time to 10 ns, which is 1.2 ns less than that of the conventional dynamic amplifier, while also reducing the operating current to less than 10% that of the static amplifier     

A New Investigation of Data Retention Time in Truly Nanoscaled DRAMs

Data retention time for ultimate DRAMs with an extremely scaled-down cell size has been investigated. The entire memory cells can be discretely categorized by two groups: leaky cells or normal cells, and the main distribution representing the normal cells shows longer than 40 s of the mean retention time. The leaky cells are mainly originated by trap-assisted gate-induced drain leakage currents depending on trap energy dispersion. Through analyses of full chip retention failure curves and interface trap density $( hbox{Dit}^{ast})$ measurements, we propose that the tail distribution will be diminished and separated from the main distribution as the cell size shrinks into a true nanoscale. As a result, the retention time is eventually to be determined by the main distribution function only.      

Voltage limiters for DRAMs with substrate-plate-electrode memorycells

To prevent substrate-plate-electrode (SPE) cell weakness due to substrate-bias voltage bounce, voltage limiters were applied to both the substrate and the sense-circuit supply source. A supply voltage V _CC bump test was introduced to evaluate their effectiveness. The voltage limiters have been implemented on an experimental 4-Mb DRAM. It was found that a wider operational margin, as compared to conventional DRAMs (without voltage limiters) having SPE cells, was achievable through the use of voltage limiters. These voltage limiters may be considered suitable for wide operational margin DRAMs with SPE cells. The substrate-bias voltage limiter, in particular, is more effective than the sense-circuit supply voltage limiter and offers a means of improving the operational margin of V_CC bump     

Circuit contributions to alpha-particle sensitivity in DRAMs

Different manufacturers' 64 K DRAM products have been studied to determine which circuit elements contribute towards the overall alpha-particle-induced soft error rate. This has shown that alpha hits on the bit lines are far and away the most important contributors to soft errors: cell, sense amplifier and peripheral circuit hits have insignificant effects. The results also indicate why bit lines are so sensitive.