基于改进型匹配网络的宽带高效率E类功放的设计

为了解决E类功放工作带宽过窄的问题,对E类功放的输入、输出匹配网络提出了一种改进方案.该方案中输出匹配网络采用微带线结构与切比雪夫低通匹配网络相结合的方法,在较宽的工作带宽内有效地抑制了谐波;并采用阻抗变换方法设计了含闭式解的宽带带通输入匹配网络,明显增强了输入匹配网络设计的灵活性.利用该方案,同时采用多谐波双向牵引技术得到功率管的最佳源阻抗和负载阻抗,基于CGH40010F功率管设计了一款应用于L波段的宽带高效率E类功放.测试结果表明,在输入功率为28dBm,漏极偏置电压VDS=28V,栅极电压VGS=-3.3V时,在整个L波段频率范围内漏极工作效率大于65%,最高达到83%,输出功率为39~41.1dBm,增益为11~13.1dB,增益平坦度为±1dB.这一结果验证了该改进方案的有效性,使得E类功放具有宽带宽、高效率的性能.     

平衡式E/F类功率放大器的设计与实现

为了解决功率放大器设计过程中存在的效率低和输入/输出端回波损耗较大的问题,设计了一种工作频率为1.5 GHz的平衡式功率放大器。通过采用3 dB定向耦合器对射频信号进行分配及合成,大大降低了输入/输出端的驻波系数,并将逆F类功率放大器的谐波控制网络引入E类功率放大器的匹配电路中。使用ADS对晶体管进行负载牵引和源牵引,得到晶体管的输入/输出阻抗,同时结合晶体管的寄生参数,在输出匹配电路中对二次谐波、三次谐波分别进行开路和短路处理,且为了进一步提高功率放大器的工作性能,在输入电路结构中抑制了二次谐波。选用GaN HEMT器件CGH40010F晶体管,利用ADS软件进行电路仿真,并采用Rogers4350b高频板材制作该功率放大器的实际测试电路板。仿真优化和实测表明：在输入功率为28 dBm时,该功率放大器的输出功率为41.54 dBm,漏极效率为76.99%,功率附加效率（power additional efficiency,PAE）达到73.59%,输入/输出端驻波系数小于2,同时具有160 MHz的高效率带宽,且最大输出功率较单管功率放大器提高了3 dB。实测结果与仿真数据有一定的误差,但仍有较好的一致性,满足设计指标要求,验证了设计方法的可行性。该设计方法具有效率高和回波损耗低的优势,提高了功率放大器的设计效率,使它在当今高效绿色节能的射频微波通信系统中具有广阔的应用前景。     

A Compact Dual-Port Multi-Band Rectifier Circuit for RF Energy Harvesting

This paper presents a compact multi-band rectifier with an improved impedance matching bandwidth. It uses a combination of п–matching network (MN) at Port-1, with a parallel connection of three cell branch MN at Port-2. The proposed impedance matching network (IMN) is adopted to reduce circuit complexity, to improve circuit performance, and power conversion efficiency (PCE) of the rectifier at low input power. The fabricated rectifier prototype operates at 0.92, 1.82, 2.1, 2.46 and 2.65 GHz covering GSM/900, GSM/1800, UMTS2100, and Wi-Fi/2.45–LTE2600. The size of the compact rectifier on the PCB board is 0.13λ_g × 0.1λ_g. The fabricated rectifier achieved an RF-to DC (radio frequency direct current) PCE of 31.8%, 24%, 22.7%, and 15%, and 14.1% for −20 dBm at the five respective measured operating frequencies. The circuit attains a peak RF-to-DC PCE of 82.3% for an input power of 3 dBm at 0.92 GHz. The proposed rectifier realizes an ambient output dc voltage of 454 mV for multi-tone input signals from the two ports. The rectifier drives a bq25504-674 power management module (PMM) to achieve 1.21 V from the two-port connection. The rectifier has the ability to exploit both frequency domain through the multi-band operation with good impedance bandwidth and a spatial domain using dual-port configuration. Hence, it is a potential candidate for various applications in radio frequency energy harvesting (RFEH) system.     

Wideband linear power amplifier for high-frequency ultrasonic coded excitation imaging

Linear power amplifiers are critical components in ultrasonic imaging systems that implement chirp-coded excitation. Bench-top commercial power amplifiers are usually used in academic laboratories for high-frequency ultrasound imaging, and the imaging performance depends greatly on these general-purpose instruments. To achieve a wide dynamic range, a power amplifier consisting of two stages is developed for chirp-coded ultrasound imaging applications through the implementation of custom-designed broadband 1:1 transformers and the optimization of feedback circuits. The amplifier has broad bandwidth (5 to 135 MHz), maintaining a linearity up to the 1-dB gain compression point (P1dB) of 41.5 dBm, allowing 16 dBm input power level at 60 MHz. The mean and the maximum values of output third-order intercept points (OIP3) are 51.8 and 53.5 dBm, respectively, between 20 and 110 MHz. With 12 dBm input power, the gain of the amplifier varies between 24 and 29 dB, offering a uniformity which would allow excitation of a 70-MHz single-element transducer with windowed chirp-coded bursts sweeping from 40 to 100 MHz. The performance in high-frequency ultrasound imaging is evaluated with a wire phantom. Echo signal-to-noise ratio (eSNR) of the designed amplifier is 7 dB better than a commercial amplifier, and spatial resolution is maintained.     

Radio-frequency front-end for 5 GHz wireless local area network transceivers

A transceiver front-end for 5 GHz wireless local area network applications has been designed and implemented in a low-cost 46 GHz f_r pure-silicon bipolar technology. The transceiver front-end adopts a superheterodyne sliding-IF architecture and consists of a down-converter, an up-converter and an LO frequency synthesiser. By exploiting a 1 bit variable-gain low-noise amplifier, the down-converter is able to provide an excellent noise figure of 4 dB while ensuring an input 1 dB compression point of 210 dBm with a current consumption of 25 mA from a 3 V supply voltage. The transmitter front-end is implemented by means of a current-reuse variable-gain up-converter. The circuit provides an output 1 dB compression point of 5.3 dBm although consuming only 45 mA from a 3 V supply voltage. Moreover, a linear-in-dB gain control characteristic is achieved over a 35 dB dynamic range. The LO frequency synthesiser is implemented by means of an integer-N phase-locked loop. It features a phase noise of 2117 dBc/Hz at 1 MHz offset from the centre frequency of 4.1 GHz and exhibits a tuning range of 1.2 GHz, from 3.47 to 4.65 GHz. The LO frequency synthesiser draws 20 mA from a 3 V supply voltage.     

Research on cryogenic behaviors of low noise amplifier with build-in PIN diode limiter

In this article we elucidate the design and fabrication of a P-band cryogenic low noise amplifier (CLNA) with built-in limiter circuit, and further studied the characteristics of PIN diode limiter at different temperature. Measurements at 75 K shows the P-band CLNA with build-in limiter has a good performance with noise figure lower than 0.5 dB, the input and output voltage standing wave ratio (VSWR) less than 1.5 and input 1 dB power compression point ?4 dBm within the band width 300 MHz. The variation of the gain within ±0.1 dB under the impact of 20 dBm input power level signals. In addition, the maximum allowed input power of the CLNA has increased from 13 dBm to 22 dBm.     

Compact and low power consumption K-band differential low-noise amplifier design using transformer feedback technique

A compact and low power consumption three-stage differential K-band low-noise amplifier (LNA) with a 10 dB differential mode gain at 25.8 GHz and a 3 dB bandwidth of 22.8-26.8 GHz by using a transformer feedback technique with standard 0.18 mum CMOS technology is presented. The minimum input and output return losses over a 3 dB bandwidth are 11 and 7 dB, respectively. Fully differential characterisations of the noise figure (NF) and the common mode rejection ratio (CMRR) are demonstrated. The obtained NF and CMRR are 4.84 dB and 23.3 dB at 25.8 GHz. The input 1 dB compression point and input third-order intercept point are 17.8 and 5 dBm, respectively. The overall power consumption is 25.6 mW. This three-stage differential LNA only occupies an area of 0.63 x 0.88 mm².     

A High Gain,Noise Cancelling 3.1-10.6 GHz CMOS LNA for UWB Application

With the rapid development of ultra-wideband communications, the design requirements of CMOS radio frequency integrated circuits have become increasingly high. Ultra-wideband (UWB) low noise amplifiers are a key component of the receiver front end. The paper designs a high power gain (S₂₁) and low noise figure (NF) common gate (CG) CMOS UWB low noise amplifier (LNA) with an operating frequency range between 3.1 GHz and 10.6 GHz. The circuit is designed by TSMC 0.13 μm RF CMOS technology. In order to achieve high gain and flat gain as well as low noise figure, the circuit uses many technologies. To improve the input impedance matching at low frequencies, the circuit uses the proposed T-match input network. To decrease the total dissipation, the circuit employs current reused technique. The circuit uses he noise cancelling technique to decreases the NF. The simulation results show a flat S₂₁>20.81 dB, the reverse isolation (S₁₂) less than -48.929 dB, NF less than 2.617 dB, the minimum noise figure (NF_min)=1.721 dB, the input return loss (S11) and output return loss (S₂₂) are both less than -14.933 dB over the frequency range of 3.1 GHz to 10.6 GHz. The proposed UWB LNA consumes 1.548 mW without buffer from a 1.2 V power supply.     

A linear operational transconductance amplifier for instrumentationapplications

A linear operational transconductance amplifier (OTA) is described that consists of a linear transconductor and a translinear current gain cell followed by three current mirrors. The proposed circuit has superior linearity and temperature characteristic when compared with the commercially available OTA. A prototype circuit with a transconductance of 50 μS has been built with discrete bipolar transistors producing a linearity error of less than ±20% over an input voltage range from -0.8 to 0.8 V. The prototype OTA circuit also exhibits a transconductance that is linearly dependent on a bias current varying over four decades with a sensitivity of 1 S/A     

An X-band, high power dielectric resonator oscillator for future military systems

A 9.0-GHz dielectric resonator oscillator (DRO), generating a CW output power of 2.5 W at room temperature, has been designed and fabricated using a high-power GaAs MESFET and a dielectric resonator (DR) in a parallel feedback configuration. The oscillator exhibited a frequency stability of better than 130 ppm, without any temperature compensation, over the range -50 degrees C to +50 degrees C. The output power varied from +35 dBm (3.2 W) at -50 degrees C to +33 dBm (2 W) at +50 degrees C. The single-sideband phase noise levels were measured and found to be -105 and -135 dBc/Hz, at 10- and 100-kHz carrier offset frequencies, respectively. The oscillator output was then fed into a single-stage high-power MESFET amplifier, resulting in a total RF power output of 6.5 W. The overall DC to RF conversion efficiency of the 6.5-W unit was approximately 15.3%     

An Automatic RMS/DC Comparator

The design of an instrument for the automatic comparison of an ac voltage with a stable dc source is described. A differential multijunction thermal converter is used as an rms/dc converter with an FET-switched input amplifier for ac/dc substitution. The output voltages of the rms/dc converter with ac and dc input voltages are sampled and stored, and the difference amplified and displayed on a panel meter or chart recorder. Accuracy is ±20 ppm of input ranges of 10-200 V at frequencies of 50 Hz-1 kHz, and maximum full scale deflection sensitivity is 0.01 percent of input range. The instrument may be used either as an rms comparator with a linear voltage scale or as a mean-square comparator with a linear power scale.     

Exploring figures of merit associated with the suboptimum operation of class-E power amplifiers

Closed-form design equations for the operation of a class-E amplifier for zero switch voltage slope and arbitrary duty cycle are derived. This approach allows an additional degree of freedom in the design of class-E amplifiers which are normally designed for 50% duty ratio. The analysis developed permits the selection of non-unique solutions where amplifier efficiency is theoretically 100% but power output capability is less than that the 50% duty ratio case would permit. To facilitate comparison between 50% (optimal) and non-50% (suboptimal) duty ratio cases, each important amplifier parameter is normalised to its corresponding optimum operation value. It is shown that by choosing a non-50% suboptimal solution, the operating frequency of a class-E amplifier can be extended. In addition, it is shown that by operating the amplifier in the suboptimal regime, other amplifier parameters, for example, transistor output capacitance or peak switch voltage, can be included along with the standard specification criteria of output power, DC supply voltage and operating frequency as additional input design specifications. Suboptimum class-E operation may have potential advantages for monolithic microwave integrated circuit realisation as lower inductance values (lower series resistance, higher self-resonance frequency, less area) may be required when compared with the results obtained for optimal class-E amplifier synthesis. The theoretical analysis conducted here was verified by harmonic balance simulation, with excellent agreement between both methods.     

Design of Relaxation Oscillator Based Ultra-wideband SFQ Amplifier for Chip to Chip Interconnection

In Rapid Signal Flux Quantum (RSFQ) logic circuits, on-chip interconnects and multichip module implementations for nearby distances have already been established. However, the flexible interconnection of two distant chips is still not achieved reliably due to impedance mismatching and attenuation. In this work, we propose a circuit that allows the usage of Passive Transmission Lines (PTLs) to transfer single-flux-quantum (SFQ) pulses between two distant chips which are separated by a distance greater than 10 cm by using 50 ?? transmission lines. For this purpose, we design an SFQ amplifier circuit to deal with impedance mismatch and attenuation problems. The circuit consists of two main parts: a relaxation oscillator (RO) circuit and an impedance transformer. The RO circuit utilizes relaxation oscillations occur in the underdamped Josephson junctions. The impedance matching circuit is an 8-section Chebyshev quarter-wave transformer and it eliminates impedance mismatching problem between the amplifier circuit and PTL. We performed circuit simulations and obtained voltage amplitude of about 600 ??V at the output of the circuit. The transformer has a broadband impedance matching with a fractional bandwidth (ratio of the bandwidth of a device to its central frequency) of 1.4 and a maximum Voltage Standing Wave Ratio (VSWR, the maximum voltage divided by minimum voltage on the transmission line) of 1.5.     

A High Gain,Noise Cancelling 2515-4900 MHz CMOS LNA for China Mobile 5G Communication Application

With the development of the times, people’s requirements for communication technology are becoming higher and higher. 4G communication technology has been unable to meet development needs, and 5G communication technology has emerged as the times require. This article proposes the design of a low-noise amplifier (LNA) that will be used in the 5G band of China Mobile Communications. A low noise amplifier for mobile 5G communication is designed based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.13 μm Radio Frequency (RF) Complementary Metal Oxide Semiconductor (CMOS) process. The LNA employs self-cascode devices in currentreuse configuration to enable lower supply voltage operation without compromising the gain. This design uses an active feedback amplifier to achieve input impedance matching, avoiding the introduction of resistive negative feedback to reduce gain. A common source (CS) amplifier is used as the input of the low noise amplifier. In order to achieve the low power consumption of LNA, current reuse technology is used to reduce power consumption. Noise cancellation techniques are used to eliminate noise. The simulation results in a maximum power gain of 22.783, the reverse isolation (S₁₂) less than -48.092 dB, noise figure (NF) less than 1.878 dB, minimum noise figure (NFmin)=1.203 dB, input return loss (S₁₁) and output return loss (S₂₂) are both less than -14.933 dB in the frequency range of 2515-4900 MHz. The proposed Ultra-wideband (UWB) LNA consumed 1.424 mW without buffer from a 1.2 V power supply.     

2.4 GHz Class-E power amplifier with transmission-line harmonic terminations

The design procedure, fabrication and measurement of a Class-E power amplifier with excellent second- and third-harmonic suppression levels are presented. A simplified design technique offering compact physical layout is proposed. With a 1.2 mm gate-width GaAs MESFET as a switching device, the amplifier is capable of delivering 19.2 dBm output power at 2.41 GHz, achieves peak PAE of 60% and drain efficiency of 69%, and exhibits 9 dB power gain when operated from a 3 V DC supply voltage. When compared to the classical Class-E two-harmonic termination amplifier, the Class-E amplifier employing three-harmonic terminations has more than 10% higher drain efficiency and 23 dB better third-harmonic suppression level. Experimental results are presented and good agreement with simulation is obtained. Further, to verify the practical implementation in communication systems, the Bluetooth-standard GFSK modulated signal is applied to both two- and three-harmonic amplifiers. The measured RMS FSK deviation error and RMS magnitude error were, for the three-harmonic case, 1.01 kHz and 0.122%, respectively, and, for the two-harmonic case, 1.09 kHz and 0.133%     

一种小型离子泵电源的设计

真空行业的迅速发展对离子泵电源提出了新的需求与挑战,小型轻量、智能控制和节能高效的离子泵电源将成为行业发展趋势。本文提出了一种通用性强的小型离子泵电源的设计方案,介绍了系统组成与拓扑结构,给出了电路参数计算和分析说明,并对该电源进行工程上的测试验证。实践表明,该电源能适配多种型号的离子泵,工作稳定可靠。     

A high-current very wide-band transconductance amplifier

A novel design approach for a high-current, very-wide-band transconductance amplifier is described. The approach is based on paralleling the input and output of complementary unipolar current-mirror cells. Each cell has a fixed current gain determined by the ratio of two resistors. A differential input voltage-to-current circuit drives the cell array. The design avoids the need for a single low-resistance current-sensing resistor and the attendant problems inherent in such resistors. Although the concept is still under development, a prototype of the cell-based transconductance amplifier was implemented with ten positive and ten negative current cells to gain some experimental familiarity with the approach in addition to providing verification of computer simulation results. The prototype transconductance amplifier is DC coupled, has a 3-dB bandwidth of about 750 kHz, and can deliver up to 35 A RMS (root mean square) at 100 kHz with an output compliance voltage of 5 V RMS. Other important characteristics such as output-load regulation and DC offsets are discussed     

Extremely low thermal noise floor, high power oscillators usingsurface transverse wave devices

This paper presents state-of-the-art results on 1-GHz surface transverse wave (STW) oscillators running at extremely high loop power levels. The high-Q single-mode STW resonators used in these designs have an insertion loss of 3.6 dB, an unloaded Q of 8000, a residual PM noise of -142 dBc/Hz at a 1-Hz carrier offset, and operate at an incident power of up to +31 dBm in the loop. Other low-Q STW resonators and coupled resonator filters (CRF), with insertion losses in the 5-9 dB range, can conveniently handle power levels in excess of two Watts. These devices were incorporated into voltage controlled oscillators (VCO's) running from a 9.6-V dc source and provide an RF output power of +23 dBm at an RF/dc efficiency of 28%. Their tuning range was 750 kHz and the PM noise floor was -180 dBc/Hz. The oscillators, stabilized with the high-Q devices and using specially designed AB-class power amplifiers, delivered an output power of +29 dBm and exhibited a PM noise floor of -184 dBc/Hz and a 1-Hz phase noise level of -17 dBc/Hz. The 1-Hz phase noise level was improved to -33 dBc/Hz using a commercially available loop amplifier. In this case, the output power was +22 dBm. In all cases studied, the loop amplifier was found to be the factor limiting the close-to-carrier oscillator phase noise performance     

Mode-locked ring laser with output pulse width of 0.4 ps

The output pulse width of a mode-locked ring laser composed of an erbium-doped fiber amplifier, Mach-Zehnder optical modulator, and optical band-pass filter depends largely on the repetition frequency and the wavelength characteristics of these optical circuit elements. In previous experiments, the output pulse width was in the order of 5 ps at a repetition frequency of 5 GHz. The principal reason was that the narrow passage band of the optical circuit elements made it extremely difficult to generate an ultra-short optical pulse. Consequently, we examined how to narrow the optical pulse width by flattening the wavelength characteristics of these optical circuit elements. Furthermore, we drove the optical modulator in the cavity using a frequency multiplier to operate at an effectively higher frequency By widening the wavelength passage band of all the devices in the optical circuit, we achieved an output pulse width of 0.4 ps at a repetition frequency of 5 GHz; the pulse peak power was more than +23 dBm, and the time-bandwidth product was 0.34. We successfully tested an ultra-short optical pulse source with an output pulse width of 0.4 ps with no external pulse compression using a mode-locked ring laser     

A new low-cost RF built-in self-test measurement for system-on-chip transceivers

This paper presents a new RF built-in self-test (BIST) measurement and a new automatic-performance-compensation network for a system-on-chip (SoC) transceiver. We built a 5-GHz low noise amplifier (LNA) with an on-chip BIST circuit using 0.18-/spl mu/m SiGe technology. The BIST-measurement circuit contains a test amplifier and RF peak detectors. The complete measurement setup contains an LNA with a BIST circuit, an external RF source, RF relays, 50-/spl Omega/ load impedance, and a dc voltmeter. The proposed BIST circuit measures input impedance, gain, noise figure, input return loss, and output signal-to-noise ratio of the LNA. The test technique utilizes the output dc-voltage measurements, and these measured values are translated to the LNA specifications such as the gain through the developed equations. The performance of the LNA was improved by using the new automatic compensation network (ACN) that adjusts the performance of the LNA with the processor in the SoC transceiver.