一种抗负压和抗共模噪声的全集成GaN电平位移电路

设计了一种基于全集成GaN工艺平台,具有抗负压、抗共模噪声的电平位移电路。相较于传统的电平位移电路,通过电路设计将驱动部分的低电压域同高侧部分电路的低电压域保持一致,实现了抗负压的功能。除此之外,针对半桥驱动开关节点的抬升、下降引起内部电容充放电并导致信号逻辑错误的问题,对高侧部分电路进行设计,实现了抗共模噪声的能力。在200 V GaN工艺下,电平位移电路将0～6 V的输入信号转换至200～206 V。仿真结果表明,该电平位移电路的上升传输延时为4.74 ns,下降传输延时为4.11 ns,抗开关节点负压为-4 V,具有100 V/ns共模噪声抑制能力。     

一种高噪声抗扰度电容式电平位移电路

设计了一种适用于GaN半桥栅驱动的高噪声抗扰度的电容式电平位移电路。在浮动电源轨发生dV/dt切换和减幅振荡时,采用去耦开关完全消除了影响输出状态的共模噪声,采用动态开关减小了电路失配引起的差模噪声。利用电容耦合技术实现了高负压容忍度、亚纳秒级延时和低功耗。采用0.18μm高压BCD工艺进行电路设计。仿真结果表明,在50 V电平转换下,该电平位移电路的共模瞬态抗扰度达到200 V/ns, 200 V/ns转换速率下的失配容忍度达到30%,负压容忍度达到-5 V,平均传输延时为0.56 ns。     

一种高速高可靠性低功耗的电平位移电路

为了满足MHz以上频率的GaN半桥栅驱动系统的应用需求,提出了一种高速高可靠性低功耗的低FOM电平位移电路。串联可控正反馈电平位移电路通过仅在转换过程中减弱正反馈力度,实现了低传输延迟和高共模噪声抗扰能力,同时采用最小短脉冲电路设计以降低功耗。该电平位移电路基于0.5 μm 80 V高压(HV) CMOS工艺进行设计与仿真验证,结果表明,电路具有960 ps的传输延时、50 V/ns的共模噪声抗扰能力和0.024 ns/(μm·V)的FOM值。     

一种高速、高共模噪声抗扰的电平位移电路

介绍了一种应用于GaN驱动的0.35μm HV CMOS工艺的高速、高共模噪声抗扰的电平位移电路。该电路采用高速电流镜和双锁存结构,并增加共模抗扰辅助电路,大大提高了传输速度和对共模噪声的抗扰能力。该高速、高共模噪声抗扰的电平位移电路主要用于驱动增强型GaN的高压半桥栅驱动。仿真结果显示该电平位移电路上升沿传输延时1.03 ns,下降沿传输延时1.15 ns,可承受GaN高压半桥栅驱动开关节点SW处电压浮动50 V/ns。     

一种高dV/dt噪声抑制的电平位移电路设计

在半桥栅驱电路中,低压域PWM控制信号需要通过电平位移电路来转换成高边浮动电压域的PWM控制信号,从而打开或关断上桥臂功率管。浮动电源轨的快速浮动会带来dV/dt噪声,影响电平位移电路信号传输的可靠性。文章在电平位移电路中分别设计了防止误关断辅助电路和防止误开启辅助电路。防止误关断辅助电路在上桥臂开启状态下检测到dV/dt噪声后,能够使电平位移电路的输出保持高电平状态,防止上桥臂功率管被误关断;防止误开启辅助电路在上桥臂关断状态下检测到dV/dt噪声后,能够使电平位移电路的输出保持低电平状态,防止上桥臂功率管被误开启。基于0.18μm BCD工艺进行仿真验证,所设计的电平位移电路开通传输延时仅为1.2 ns,具备100 V/ns的dV/dt噪声抑制能力。     

一种高速高共模瞬态抗扰度电平位移电路

设计了一种适用于GaN栅驱动的高速、高共模瞬态抗扰度的电平位移电路。电路受PWM信号和短脉冲协同控制,利用短脉冲控制的加速电路提升了电平转换速度。在浮动电源轨高速切换和减幅振荡过程中,电路内部对地寄生电容的充放电会导致输出逻辑错误。针对此问题,采用一种高速、低功耗的交叉控制式噪声屏蔽电路,实现了极高的共模瞬态抗扰度。采用0.35μm高压CMOS工艺进行电路设计。仿真结果表明,在100 V电平转换情况下,该电平位移电路的平均传输延时为1.58 ns,延时失配小于100 ps,共模瞬态抗扰度达到200 V/ns。     

用于GaN半桥驱动器的高速电平移位电路

设计了一种GaN半桥驱动器高性能电平移位电路,一方面采用短脉冲控制的高速镜像噪声电流与噪声电流相互抵消的方法消除共模噪声,另一方面采用脉冲宽度调制(PWM)控制的正反馈互锁电路,该电路不含RC滤波,用来消除由于工艺偏差造成的差模噪声,以保证输出信号稳定。抗负压电路采用降压电平移位电路实时监测高侧电压浮动状态并反馈回自举充电回路,使充电时间避开负压时间。在0.18μm 85 V BCD工艺下完成设计,工作频率达到5 MHz,上升时间为4.1 ns,下降时间为3.8 ns,满足高频GaN栅驱动应用需求。     

基于40 nm CMOS工艺的电平转换器的设计及优化

电平转换器可以作为1.1V核心电压和3.3V输入输出电压之间的高速接口.优化的电压上升转换器使用2.5V厚氧化层栅零阈值电压nMOS管保护1.1V薄氧化层栅nMOS器件,在输入电压低至0.7V时仍可正常工作;此外,在六种不同工作情况下电路性能良好.3.3 V nMOS器件作为优化电平下降转换器的上拉和下拉器件,它们的供电电压是1.1V,栅压范围从0V到3.3V.电平下降转换器没有最小核心电压限制,上升传输延时0.111 ns,下降传输延时0.121 ns.电平转换器经过结构优化后,可以成功应用到40 nm CMOS工艺的I/O库的输入输出单元中,作为低功耗、高速接口.     

高压栅级驱动器

高压栅级驱动器FAN7387，针对镇流器、SMPS和半桥逆变器设计，是唯一带有用于死区时间控制外部引脚的高压栅极驱动器（HVIC）。这款HVIC采用创新的噪声消除技术，高边驱动器运作的负Vs摆幅高达-9．8V，这种特性可保护IC免受负噪声影响，且有更强的噪声免疫能力。     

基于高压BCD工艺的内集成自举电路

设计了一款基于高压BCD工艺的内集成MOS自举电路,将其应用于高压集成电路(HVIC)。对传统的内集成MOS自举电路进行改进,该改进版内置MOS自举电路集成升压控制模块,实现在HVIC通电后屏蔽HVIC输入信号,并通过集成的升压电路将自举电容电压充到预期值,解决了以往使用传统的内置MOS自举功能时,因充电速度慢、充电电压低所导致的触发HVIC欠压保护和电器频繁停机问题。基于SMIC 3μm BCD工艺对所设计的自举电路的HVIC进行流片验证。测试结果表明,升压电路将HVIC供电电压从15 V升高至16.4 V,自举电容电压可达到预期值,同时实现了替代外接自举二极管或通过SOI工艺内置自举二极管的自举功能。     

G/G/m queueing system with discouragement via diffusion approximation

This paper provides an approximation technique for a G/G^y/m queueing system with discouragement. The approximation is based on the theory of diffusion, depending on the means and variances of interarrival time and service time distributions. The arriving customers are assumed to be discouraged when a large number of customers are present in the system. The expressions for the probability of there being n customers in the system and the mean number of customers in the system, are obtained.     

Consecutive-k, r-out-of-n:DFM systems

A dual failure mode (DFM) system is a system whose components are subject to two different kinds of failure (three-state units). In this paper, a new system (the consecutive-k, r-out-of-n:DFM system) is introduced by considering an extension of the well-known and much studied consecutive-k-out-of-n:F system to a dual failure mode environment. Recursive formulae are provided for the evaluation of the reliability of a consecutive-k, r-out-of-n:DFM system with unequal component failure probabilities. Finally, some simple upper and lower reliability bounds are established which provide quite adequate approximations, at least for highly reliable systems.     

Bounds for reliability of k-within connected-(r, s)-out-of-(m, n) failure systems

A k-within linear connected-(r, s)-out-of-(m, n) failure system is a two-dimensional grid whose components are ordered like the elements of an (m, n)-matrix. A k-within circular connected-(r, s)-out-of (m, n) failure system consists of the intersection points of m circles centered at the same point with n rays starting from that point and crossing the circles. The components of both systems either operate or fail. By definition, a k-within (linear or circular) connected-(r, s)-out-of-(m, n) failure system fails if at least one (r, s)-submatrix contains k or more failed components. These systems are used as mathematical models for design and operation of many engineering systems. For systems with statistically independent and identically distributed components, a lower and upper bound of system reliability are derived using improved Bonferroni inequalities. These bounds are easy to compute and provide good estimates for system reliability. New bounds for the reliability of other connected-(r, s)-out-of-(m, n) failure systems existing in the current literature are also obtained. Several failure systems with various values of the parameters k, r, s, m, n and p are used as numerical examples for comparison and illustrative purposes.     

p-n heterojunctions

A classical kinetic emission model coupled with an assumed energy band diagram which includes the effects of a discontinuity in the electron affinity, effective mass, permittivity and the energy gap at the junction interface is used as the basis for an analysis of the static current-voltage characteristic of the abrupt p-n heterojunction. The derived characteristic is then used to determine regions of quasi-equilibrium within the depletion layer and to predict the position dependence of the quasi-Femri levels.

Two distinct modes of operation are predicted for the heterojunctions I–V characteristic: Metal-semiconductor type operation where the current is limited by the ability of the carriers to surmount the potential barrier at the junction interface and homojunction type operation where the current is limited by the ability of the carriers to diffuse away from the junction depletion region. The predicted extrapolated saturation current for the former type of operation, is in general, significantly less than that for the latter. The position dependence of the quasi-Fermi levels is also different for the two types of operation. For metal-semiconductor type operation a drop in the quasi-Fermi level across the depletion layer is expected, whereas for homodiode type operation there is a negligible variation of the quasi-Fermi level in this region.

The heterojunction I–V characteristic presented here, which differs significantly from previous models, agrees favourably with experimental data on Ge-GaAs heterojunctions reported in the literature and with others recently fabricated by the present authors.     

A VLSI structure forX(modm) operation

High-computing speed and modularity have made RNS-based arithmetic processors attractive for a long time, especially in signal processing, where additions and multiplications are very frequent. The VLSI technology renewed this interest because RNS-based circuits are becoming more feasible; however, intermodular operations degradate their performance and a great effort results on this topic. In this paper, we deal with the problem of performing the basic operationX(modm), that is the remainder of the integer divisionX/m, for large values of the integerX, following an approximating and correcting approach, which guarantees the correctness of the result.We also define a structure to computeX(modm) by means of few fast VLSI binary multipliers, which is exemplified for 32-bit long numbers, obtaining a total response time lower than 200 nsec. Furthermore, such a structure is evaluated in terms of VLSI complexity and area and time figuresA=(n ² T _m ² ) andT=(T _M ) for the parameterT _M in are derived. A simple positional-to-residue converter is finally presented, based on this structure; it improves some complexity results previously obtained by authors.This work has been supported by the National Program on Solid-State Electronics and Devices of the Italian National Research Council.     

The maximal PN sequences over GF(p)

In this paper analysis of the maximal pseudorandom sequences (PN sequences) over a Galois Field GF(p) is given. The first part of the paper deals with the properties of the sequences of vectors generated over GF(p). In the second part the autocorrelation function of the pseudorandom sequences is discussed.     

Structural and interfacial properties of high-k HfOxNy gate dielectric films

The thermal stability and interfacial characteristics for hafnium oxynitride (HfO_xN_y) gate dielectrics formed on Si (1 0 0) by plasma oxidation of sputtered HfN films have been investigated. X-ray diffraction results show that the crystallization temperature of nitrogen-incorporated HfO₂ films increases compared to HfO₂ films. Analyses by X-ray photoelectron spectroscopy confirm the nitrogen incorporation in the as-deposited sample and nitrogen substitution by oxygen in the annealed species. Results of FTIR characterization indicate that the growth of the interfacial SiO₂ layer is suppressed in HfO_xN_y films compared to HfO₂ films annealed in N₂ ambient. The growth mechanism of the interfacial layer is discussed in detail.     

In situ TEM/SEM electronic/mechanical characterization of nano material with MEMS chip

Our investigation of in situ observations on electronic and mechanical properties of nano materials using a scanning electron microscope （SEM） and a transmission electron microscope （TEM） with the help of tradi- tional micro-electro-mechanical system （MEMS） technology has been reviewed. Thanks to the stability, continuity and controllability of the loading force from the electrostatic actuator and the sensitivity of the sensor beam, a MEMS tensile testing chip for accurate tensile testing in the nano scale is obtained. Based on the MEMS chips, the scale effect of Young＇s modulus in silicon has been studied and confirmed directly in a tensile experiment using a transmission electron microscope. Employing the nanomanipulation technology and FIB technology, Cu and SiC nanowires have been integrated into the tensile testing device and their mechanical, electronic properties under different stress have been achieved, simultaneously. All these will aid in better understanding the nano effects and contribute to the designation and application in nano devices.