采用分段式自适应PWM/PFM调制的Buck型DC-DC转换器设计北大核心

为了在轻重负载条件下获得更高的转换效率，采用分段式结构和导通电阻更小的NMOS作为输入级，并采用PWM/PFM双调制方式，设计了一种Buck型DC-DC转换器。为解决PWM/PFM调制信号切换问题，采用零电流检测方式进行切换。利用断续导通模式(DCM)和连续导通模式(CCM)下端NMOS管导通时电感电压的不同，检测下端NMOS在导通时电感电压大于零的周期。当电感电压大于零的周期大于2时，则处于DCM模式并自动采用PFM调制模式，关闭一部分功率管以减小开关频率和功率管寄生电容，优化轻载效率；反之则处于CCM模式并采用PWM调制。仿真结果表明，在负载电流10～1 000 mA范围内，该电路可以在两种调制模式平稳切换，在800 mA时峰值效率可提升到96%以上。     

脉冲频率调制（PFM）

脉冲频率调制（PFM）是一种转换方法,通常被应用于DC-DC转换器来提高轻负载效率。在TI提供的产品说明书中,PFM也被称作“节电”模式。工作在节电模式下的转换器在轻负载电流条件下使用PFM模式,在较重负载电流条件下使用脉冲宽度调制（PWM）模式。这种工作模式使转换器可以在宽泛的电流输出范围内均保持极高的效率。     

PWM/PFM混合控制DC-DC变换器芯片的设计

结合脉冲宽度调制(PWM)和脉冲频率调制(PFM)功率损耗特点,提出了一种降压型PWM/PFM混合控制DC-DC变换器芯片的电路结构,大大提高了全负载范围转换效率。重点讨论了混合控制策略和PWM/PFM切换电路的设计。Hspice模拟仿真结果验证了设计的正确性。     

一种具有750mA输出电流,双模式PWM/PFM控制的高效率直流-直流降压转换器

提出了一种输出电流可达750mA,脉宽调制（PWM）和变频调制（PFM）双模式控制的,高效率、高稳定性直流-直流降压转换器.该转换器在负载电流大于80mA时,采用开关频率为1MHz的PWM工作模式;在负载电流小于80mA时,采用开关频率减小和静态电流降低的PFM工作模式,实现了在整个负载电流变化范围（0.02~750mA）内,转换器均保持高效率.而且采用一种快速响应的电压模式控制结构,达到了优异的线性和负载调整特性.芯片采用CSMC公司0.5μm CMOS 2P3M混合信号工艺物理实现.测试结果表明,该电路可根据负载的变化在PWM和PFM模式下自动切换.最大转换效率达96.5%;当负载电流为0.02mA时,转换效率大于55%.该芯片特别适合电池供电的移动系统使用.     

一种宽负载高效率Buck转换器设计

本文提出了一种双模式调制技术,以提高宽负载范围内降压型DC-DC转换器的转换效率。采用自适应导通时间电路(AOT)和斜坡信号V_RAMP产生电路来维持转换器连续导通时间(CCM)工作模式下开关频率基本稳定;利用过零检测电路来检测电感电流,当电感电流过零时,能及时关断续流管,降低开关损耗,进一步提升轻载转换效率。该DC-DC基于SMIC 0.18 um BCD工艺进行电路仿真验证,该电路可在0～3A宽负载范围内正常工作,在输入电压3～5V范围内,PFM模式下输出电压纹波小于5.2mV,1m A负载下转换效率为87.37%。在PWM模式下输出电压纹波小于2.8mV,3A负载下最低转换效率为84.24%。峰值效率可达94.91%,全负载范围内转换效率大于84%。     

数字控制PFM/PWM混合型DC-DC开关电源

结合脉冲频率调制(PFM)和脉冲宽度调制(PWM)的特点,设计了一种混合型的降压DC-DC控制器,提高了全负载情况下的效率,并进行了多种低功耗设计,轻负载时效率提高。控制器的PWM采用数字化PID控制,PFM采用电压电流的双环反馈控制,在1mA~2A的宽负载范围内效率为80%~92%。     

一种高效率升压型ＤＣ－ＤＣ转换器设计

设计了一种基于PWM/PFM调制模式的全负载高效率升压型DC-DC转换器。根据负载不同,实现PWM和PFM模式的自动切换。轻载时,进入PFM模式,降低开关损耗,并加入电感峰值限流,减小输出电压纹波。在DCM状态下,利用休眠模式电路,降低静态功耗,同时提出一种抗振铃电路,进一步提升轻载转换效率。芯片实测结果表明,1mA轻载条件下,效率依然达到91.6%,输出电压纹波约为6.6 mV。全负载最高效率可以达到93.1%。     

一种具有750mA输出电流，双模式PWM/PFM控制的高效率直流-直流降压转换器

提出了一种输m电流可达750mA,脉宽调制(PwM)和变频调制(PFM)双模式控制的,高效率、高稳定性直流.直流降压转换器.该转换器在负载电流大于80mA时,采用开关频率为lMHz的PwM工作模式;在负载电流小于80mA时,采用开天频率减小和静态电流降低的PFM工作模式,实现了在整个负载电流变化范围(0.02～750mA)内,转换器均保持高效率.而且采用一种快速响应的电压模式控制结构,达到了优异的线性和负载调整特性.芯片采用CSMC公司0.5μm CMOS 2P3M混合信号上艺物理实现.测试结果表明,该电路可根据负载的变化在PWM和PFM模式下自动切换.最大转换效率达96.5%;当负载电流为0.02mA时,转换效率大于55%.该芯片特别适合电池供电的移动系统使用.     

一种具有750mA输出电流,双模式PWM/PFM控制的高效率直流一直流降压转换器

提出了一种输m电流可达750mA,脉宽调制(PwM)和变频调制(PFM)双模式控制的,高效率、高稳定性直流.直流降压转换器.该转换器在负载电流大于80mA时,采用开关频率为lMHz的PwM工作模式;在负载电流小于80mA时,采用开天频率减小和静态电流降低的PFM工作模式,实现了在整个负载电流变化范围(0.02～750mA)内,转换器均保持高效率.而且采用一种快速响应的电压模式控制结构,达到了优异的线性和负载调整特性.芯片采用CSMC公司0.5μm CMOS 2P3M混合信号上艺物理实现.测试结果表明,该电路可根据负载的变化在PWM和PFM模式下自动切换.最大转换效率达96.5%;当负载电流为0.02mA时,转换效率大于55%.该芯片特别适合电池供电的移动系统使用.     

可实现DVS的单电感双输出降压型直流-直流转换器

设计了一款单电感双输出(SIDO)的降压型直流-直流转换器,一个输出电压可以进行动态电压转换,在0.725～1.2V直接变化,另一输出电压可实现1.2V和1.8V,两路输出最大可实现500mA负载电流。转换器根据负载的不同在脉冲宽度调制(PWM)和脉冲频率调制(PFM)之间自动切换。采用死区时间自适应调整的技术来提高系统的转换效率,分段开关则用来降低输出端毛刺。基于TSMC0.25μm CMOS工艺,测试结果证明该系统输出电压纹波低、毛刺小,系统峰值效率可达90%。     

单片降压型DC-DC转换器的控制电路设计

基于峰值电流检测脉宽调制技术原理,设计了一种新颖的应用于单片降压型DC-DC转换器的控制电路。针对峰值电流采样和PWM比较器电路技术,提出了一种新颖的电路结构。其中,PWM比较器和逻辑及驱动电路由升压电路驱动,节省了一个电平转换电路,降低了电路功耗;PWM比较器直接对功率管和镜像管电流采样,无需使用运算放大器,简化了电路结构。采用华虹宏力BCD350GE工艺进行设计,流片测试表明,电路可实现3V到36 V宽幅输入,500 mA满载输出。在输入24 V电压,输出3.3 V电压时,纹波为2.3 mV。     

A Dual-Mode Step-up DC/DC Converter IC with Current-Limiting and EMI Reduction Techniques

This paper presents a novel dual-mode step-up （boost） DC/DC converter. Pulse-frequency modulation （PFM） is used to improve the efficiency at light load. This converter can operate between pulse-width modulation （PWM） and pulse-frequency modulation. The converter will operate in PFM mode at light load and in PWM mode at heavy load. The maximum conversion efficiency of this converter is 96%. The conversion efficiency is greatly improved when load current is below 100 mA. Additionally, a soft-start circuit and a variable-sawtooth frequency circuit are proposed in this paper. The former is used to avoid the large switching current at the start up of the converter and the latter is utilized to reduce the EMI of the converter.     

A dual-mode fast-transient average-current-mode buck converter without slope-compensation

A dual-mode fast-transient average-current-mode buck converter without slope-compensation is proposed in this paper. The benefits of the average-current-mode are fast-transient response, simple compensation design, and no requirement for slope-compensation, furthermore, that minimizes some power management problems, such as EMI, size, design complexity, and cost. Average-current-mode control employs two loop control methods, an inner loop for current and an outer one for voltage. The proposed buck converter using the current-sensing and average-current-mode control techniques can be stable even if the duty cycle is greater than 50%. Also, adaptively switch between pulse-width modulation (PWM) and pulse-frequency modulation (PFM) is operated with high conversion efficiency. Under light load condition, the proposed buck converter enters PFM mode to decrease the output ripple. Even more, switching PWM mode realizes a smooth transition under heavy load condition. Therefore, PFM is used to improve the efficiency at light load. Dual-mode buck converter has high conversion efficiency over a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 μm CMOS 2P4M processes, the total chip area is 1.45×1.11 mm². Maximum output current is 450 mA at the output voltage 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 0.8-2.8 V. Maximum transient response is less than 10 μs. Finally, the theoretical analysis is verified to be correct by simulations and experiments.     

A High Efficiency Dual-Mode Buck Converter IC For Portable Applications

This paper presents the design of a novel wide output current range dual-mode dc to dc step-down (Buck) switching regulator/converter. The converter can adaptively switch between pulsewidth modulation (PWM) and pulse-frequency modulation (PFM) both with very high conversion efficiency. Under light load condition the converter enters PFM mode. The function of closing internal idle circuits is implemented to save unnecessary switching losses. The converter can be switched to PWM mode when the load current is greater than 100 mA. Soft start operation is designed to eliminate the excess large current at the start up of the regulator. The chip has been fabricated with a TSMC 2P4M 0.35 mum polycide CMOS process. The range of the operation voltage is from 2.7 to 5 V, which is suitable for single-cell lithium-ion battery supply applications. The maximum conversion efficiency is 95% at 50 mA load current. Above 85 % conversion efficiency can be reached for load current from 3 to 460 mA.     

A 4-/spl mu/a quiescent-current dual-mode digitally controlled buck converter IC for cellular phone applications

This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm/sup 2/ in 0.25-/spl mu/m CMOS. Very high efficiencies are achieved over a load range of 0.1-400 mA. Measured quiescent current in PFM mode is 4 /spl mu/A.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

DCM,FSM,dead time and width controllers for a high frequency high efficiency buck DC-DC converter over a wide load range

This paper presents a width controller,a dead time controller,a discontinuous current mode(DCM) controller and a frequency skipping modulation(FSM) controller for a high frequency high efficiency buck DC-DC converter. To improve the efficiency over a wide load range,especially at high switching frequency,the dead time controller and width controller are applied to enhance the high load efficiency,while the DCM controller and FSM controller are proposed to increase the light load efficiency.The proposed D...     

An ultra-low power CMOS DC–DC buck converter with double-chain digital PWM technique

In present-day integrated digital circuits are become attractive choice for the DC–DC buck converters. This paper proposes a novel approach of CMOS DC–DC buck converter with double-chain digital pulse width modulation (PWM) for ultra-low power applications. The proposed digital PWM architecture consists of double delay lines which is to reduce power consumption and improves ripple voltage with the resolution. An algorithm is proposed that describes the operation of digital PWM. The double chain digital PWM is implemented and analyzed in cadence platform using commercial 180 nm TSMC design kit. The promising results reveals that the power consumption is reduces up to 1.16 µW with occupies less area under the operating frequency of 100 kHz. The DC–DC buck converter with proposed PWM achieves peak efficiency of 92.6% including a load current range of 4–10 mA. This proposed digital PWM method demonstrates its ability to minimize the ripple voltage by 49% and enables to DC–DC converter for compose in a compact chip area as compared to conventional converters. Measured and Simulated power efficiency are made good agreement with each other.