CMOS电路结构中的闩锁效应及其防止措施研究

CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图、工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应关键技术方案。     

CMOS电路结构中的闩锁效应及其防止措施研究

CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。文章首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图设计和工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应的关键技术方案。     

一种Bipolar结构中的闩锁效应

闩锁是集成电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致整个器件失效。文章较为详细地阐述了一种Bipolar结构中常见的闩锁效应,并和常见CMOS结构中的闩锁效应做了对比。分析了该闩锁效应的产生机理,提取了用于分析闩锁效应的等效模型,给出了产生闩锁效应的必要条件与闩锁的触发方式。通过对这些条件的分析表明,只要让Bipolar结构工作在安全区,此类闩锁效应是可以避免的。这可以通过版图设计和工艺技术来实现。文章最后给出了防止闩锁效应的关键设计技术。     

CMOS与BIPOLAR IC兼容工艺的研究

本文介绍n阱CMOS与BIPOlAR集成电路兼容工艺。在CMOS集成电路工艺的基础上增加一次双极晶体管的基区注入,CMOS特性不改变。     

SiGe HBT的Mextram 504模型温度参数提取与模型改进

针对IMEC 0.13μm准自对准SiGe BiCMOS工艺制成的基区Ge组分二阶分布结构SiGe异质结双极晶体管,在25～125℃温度范围内,对其进行了包括Early电压,Gummel图形等在内的完整双极晶体管特性曲线测量,提取了该器件在25～125℃范围内的温度可变Mextram 504模型参数.在此基础上,为Mextram 504模型对0.13μm基区Ge组分二阶分布SiGe异质结双极晶体管探索了完整的模型提取方案.提出了对Mextram 504模型温度参数提取方法的改进,优化了提取流程.对SiGe异质结双极晶体管雪崩电流受温度影响的特性进行了讨论,为Mextram模型提出了雪崩外延层的有效厚度的温度变化经验公式和新的雪崩电流温度变化参数,提高了Mextram模型对不同温度下SiGe双极型晶体管进行模拟仿真的精确度.     

由栅氧损伤引起闩锁效应的失效分析

随着MOS器件特征尺寸的缩小和栅氧化层厚度的减薄,栅氧损伤成为MOS集成电路在实际应用中的主要失效模式之一.闩锁是CMOS集成电路结构所固有的寄生效应,寄生的可控硅结构一旦被特定条件触发,会在电源与地之间形成大电流通路,导致整个器件失效.对一例由栅氧损伤引起器件闩锁效应的失效进行分析.通过微光显微镜(EMMI)技术和激光诱导阻值变化(OBIRCH)技术进行失效定位,在电路板级通信状态下进行闩锁效应复现及验证.最后通过分析损伤所在的电路功能和器件结构,阐述闩锁效应形成的机理.     

低温硅双极晶体管基区优化设计

常规双极晶体管在７７Ｋ下电流增益和频率性能都严重退化。本文首先分析了低温双极晶体管基区Ｇｕｍｍｅｌ数，基区方块电阻，渡越时间和穿通电压等参数与温度及基区掺杂的关系，然后讨论了低温双极器件基区的优化设计问题。     

硅双极晶体管直流特性低温效应的研究

从理论和实验上研究了硅双极晶体管直流特性的低温效应,建立了不同发射结结深的硅双极晶体管电流增益的温度模型,讨论了不同工作电流下H_(FE)的温度特性,并分析了大电流下基区展宽效应的温度关系。     

CMOS集成电路闩锁效应抑制技术

闩锁效应是CMOS集成电路在实际应用中失效的主要原因之一,而且随着器件特征尺寸越来越小,使得CMOS电路结构中的闩锁效应日益突出。文章以P阱CMOS反相器为例,从CMOS集成电路的工艺结构出发,采用可控硅等效电路模型,较为详细地分析了闩锁效应的形成机理,给出了闩锁效应产生的三个基本条件,并从版图设计和工艺设计两方面总结了几种抑制闩锁效应的关键技术。     

SOI LIGBT抗闩锁效应的研究与进展

概述了绝缘层上硅横向绝缘栅双极晶体管(SOI LIGBT)抗闩锁结构的改进历程,介绍了从早期改进的p阱深p+欧姆接触SOI LIGBT结构到后来的中间阴极SOI LIGBT、埋栅SOILIGBT、双沟道SOI LIGBT、槽栅阳极短路射频SOI LIGBT等改进结构;阐述了一些结构在抗闩锁方面的改善情况,总结指出抑制闩锁效应发生的根本出发点是通过降低p基区电阻的阻值或减小流过p基区电阻的电流来削弱或者切断寄生双极晶体管之间的正反馈耦合。     

Latchup model for the parasitic p-n-p-n path in bulk CMOS

The inherent parasitic bipolar transistors and p-n-p-n paths in monolithic CMOS circuits can be undesirably triggered into the low resistance and high current state, i.e., latchup. To ensure the safe operation for the future scaled CMOS circuits, an accurate latchup model is required for design optimization. A modified lumped resistance model has been developed which is shown to accurately predict the latchup characteristics provided the device parameters are accurately measured and reflect those at the latchup state. The model includes the spreading resistance effect in the substrate by a resistor network and it is shown to be critical in the latch-up characterization. Experimental data that supports this model is presented. The reversed layouts in CMOS circuits have been shown to greatly improve the latchup holding current. The dynamic characterization of latchup, caused by voltage overshoot at the input terminals, has also been characterized. It is shown that a minimum turn-on time for the latchup triggering exists and is governed by the base transit time in the lateral transistor with an enhanced diffusion coefficient from the high injection effect.     

集成电路闩锁效应测试

CMOS制程是现今集成电路产品所采用的主流制程。闩锁效应(Latch-up)是指CMOS器件中寄生硅控整流器(SCR)被触发导通后,所引发的正反馈过电流现象。过电流的持续增加将使集成电路产品烧毁。闩锁效应已成为CMOS集成电路在实际应用中主要失效的原因之一。在国际上,EIA/JEDEC协会在1997年也制订出了半静态的闩锁效应测量标准,但只作为草案,并没有正式作为标准公布。我们国家在这方面还没有一个统一的测量标准,大家都是在JEDEC标准的指导下进行测量。文章针对目前国际上通行的闩锁效应测试方法作一个简要的介绍和研究。     

A bipolar load CMOS SRAM cell for embedded applications

This paper presents a new SRAM cell concept which offers cell scaling without requiring complicated, specialized processing technology. The proposed cell utilizes a bipolar transistor in an open-base (base is floating) configuration as a simple means of realizing a high impedance load element. The Bipolar Transistor Load (BTL) is designed such that its open base current (the holding current) is always large enough to compensate for the NMOS pull-down transistor leakage current. The load holding current and the pull-down transistor leakage current are based on the same physical mechanism, namely thermal generation, as a result the load exhibits current tracking properties over varying process and temperature conditions. The cell size is 72 μm² with typical 0.8 μm design rules, which is about a 60% reduction as compared to a standard 6-T full CMOS cell. The operating properties of the BTL cell were studied analytically and characterized experimentally. The BTL SRAM module can be easily integrated as part of any CMOS process with minimal additional processing steps     

Dramatic increases in latchup holding voltage for sub-0.5 μmCMOS using shallow S/D junctions

Large increases in the latchup holding voltage are demonstrated with the use of shallow source-drain junctions in a sub-0.5 μm CMOS process. Holding voltages well above the supply voltage for 2 μm n ⁺/p⁺ spacings are demonstrated without the use of complex processes such as retrograde wells or buried layers. SIMS data is presented to verify the reduction in junction depths to 0.15 μm for the p⁺/n-well and 0.14 μm for the n⁺/p-well junction. The improvement in holding voltage is attributed to reductions in parasitic bipolar transistor gains, due to the increase in base width. Well behaved transistor characteristics are presented using the shallow junction technology     

SPICE modeling and quick estimation of MOSFET mismatch based onBSIM3 model and parametric tests

This paper reports a MOS transistor mismatch model applicable for submicron CMOS technologies and developed based on the industry standard BSLM3v3 model. A simple and unified expression was derived to formulate the effect of MOSFET mismatch on drain current variance. A way to quickly estimate the drain current mismatch was also suggested. The model has been integrated into HSPICE, and results obtained from simulation and measurements were compared     

Parasitic SCR between a Schottky diode and an adjacent transistor

A Schottky diode and an adjacent transistor in integrated circuits may show parasitic silicon controlled rectifier (SCR) latching. This parasitic effect must be taken into account by circuit designers. If the SCR latches, an undesirable electrical short is formed between the Schottky diode and the emitter of the transistor. In this paper the conditions are investigated under which the parasitic SCR can switch. Experimental data are presented which show the validity of the theoretical considerations. Recommendations are given on how to suppress parasitic SCR latching.     

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.