A 100-MHz CMOS wide-band IF amplifier

When the data rates of communication systems increase, wideband IF amplifiers are needed. It is also possible to use a single wideband intermediate frequency (IF) amplifier for a radio band with several narrow-band channels of varying strengths. The linearity is then critical, if intermodulation products are not to disturb weak channels. We try to find a topology for this new amplifier application, suitable for integration in a standard CMOS process. To get low distortion, we use an output stage with high linearity, which is further linearized by feedback in a double-nested Miller configuration. A 0.8-μm standard CMOS IF amplifier design with low distortion up to 20 MHz is presented     

DC-coupled IF stage design for a 900-MHz ISM receiver

This paper presents a DC-coupled 900-MHz ISM band RF front-end for a short-range wireless receiver. The front-end, fabricated in a 0.5-/spl mu/m CMOS process, is intended as a test vehicle to verify the proposed DC-coupled topology. In this topology, a low-frequency feedback circuit suppresses the DC offset and low-frequency noise at the mixer output. The DC-coupled topology is compared with traditional AC coupling. We show that there is a tradeoff between bandwidth and midband loss in a fully integrated AC-coupled system. The proposed DC-coupling technique does not impose this tradeoff. The DC-coupled topology was verified via simulation and measurements from the test vehicle.     

A fully integrated 900-MHz CMOS wireless receiver with on-chip RF and IF filters and 79-dB image rejection

A monolithic 900-MHz CMOS wireless receiver with on-chip RF and IF filters and a fully integrated fractional-N synthesizer is presented. Implemented in a standard 0.5-/spl mu/m CMOS process and without any off-chip component, the complete receiver has a measured image rejection of 79 dB, a sensitivity of -90 dBm, an IIP3 of -24 dBm, and a noise figure of 22 dB with a power of 227 mW and a chip area of 5.7 mm/sup 2/. The synthesizer achieves a phase noise of -118 dBc/Hz at 600 kHz offset and a settling time of less than 150 /spl mu/s.     

A 4.5-mW 900-MHz CMOS receiver for wireless paging

An ultralow-power 900-MHz receiver implemented on a single CMOS chip is intended for use in FLEX wireless paging. The receiver uses an indirect conversion to zero intermediate frequency (IF) to suppress the flicker noise corner in the second mixer to less than 1 kHz. Various techniques for low-power design, most of them unique to CMOS, are presented, with theoretical support and experimental verifications. The receiver, fabricated in a 0.25-μm standard CMOS process, achieves 7.4-dS noise figure at 1.6 kHz with -25-dBm IIP3 on a 1.5 V supply. The voltage-controlled oscillator (VCO) has a phase noise of -98 dBc/Hz at 25 kHz offset. The nominal receiver bias current of 3 mA is higher than the expected 2 mA because of unanticipated losses in coupling capacitors     

A 10.7-MHz CMOS SC radio IF filter using orthogonal hardwaremodulation

FM radio receivers require an IF filter for channel selection, customarily set at an IF center frequency of 10.7 MHz. Up until now, the limitations of integrated radio selectivity filters in terms of power dissipation, dynamic range, and cost are such that it is still required to use an external ceramic 10.7-MHz bandpass filter. This paper demonstrates a CMOS switched-capacitor IF filter that can be integrated with most of the rest of the FM receiver, eliminating external components and printed circuit board area. This is made possible through a combination of two techniques: orthogonal hardware modulation, and delta-charge redistribution. It exhibits a tightly controlled center frequency with a Q of 55 and also contains a programmable gain. The filter occupies an area of 0.7 mm² in a 0.6 μm CMOS process with poly-poly capacitors. The new filter requires only 16 mW of power, and this is offset by elimination of the power needed in current designs to drive off-chip filters     

A 900-MHz dual-conversion low-IF GSM receiver in 0.35-μm CMOS

A low-power fully integrated GSM receiver is developed in 0.35-μm CMOS. This receiver uses dual conversion with a low IF of 140 kHz. This arrangement lessens the impact of the flicker noise. The first IF of 190 MHz best tolerates blocking signals. The receiver includes all of the circuits for analog channel selection, image rejection, and more than 100-dB controllable gain. The receiver alone consumes 22 mA from a 2.5-V supply, to give a noise figure of 5 dB, and input IP3 of -16 dBm. A single frequency synthesizer generates both LO frequencies. The integrated VCO with on-chip resonator and buffers consume another 8 mA, and meets GSM phase-noise specifications     

An 8-bit 100-MHz CMOS linear interpolation DAC

An 8-bit 100-MHz CMOS linear interpolation digital-to-analog converter (DAC) is presented. It applies a time-interleaved structure on an 8-bit binary-weighted DAC, using 16 evenly skewed clocks generated by a voltage-controlled delay line to realize the linear interpolation function. The linear interpolation increases the attenuation of the DAC's image components. The requirement for the analog reconstruction filter is, therefore, greatly relaxed. The DAC aims for the single-chip integration of a wireless transmitter. The chip was fabricated in a 3.3-V 0.35-/spl mu/m double-poly triple-metal CMOS process. The core size of the chip is 0.67 mm /spl times/ 0.67 mm, and the total power consumption is 54.5 mW with 3.3-V power supplies. The attenuation (in decibels) of image components is doubled compared with a conventional DAC.     

An 8-bit 150-MHz CMOS A/D converter

This paper describes an 8-bit 5-stage pipelined and interleaved analog-to-digital converter that performs analog processing only by means of open-loop circuits such as differential pairs and source followers to achieve a high conversion rate. The concept of sliding interpolation is proposed to obviate the need for a large number of comparators or interstage digital-to-analog converters and residue amplifiers. The pipelining scheme incorporates distributed sampling between the stages so as to relax the linearity-speed tradeoffs in the sample-and-hold circuits, A clock edge reassignment technique is also introduced that suppresses timing mismatches in interleaved systems, and a punctured interpolation method is proposed that reduces the integral nonlinearity error with negligible speed or power penalty. Fabricated in a 0.6-μm CMOS technology, the converter achieves differential and integral nonlinearities of 0.62 and 1.24 LSB, respectively, and a signal-to-(noise+distortion) ratio of 43.7 dB at a sampling rate of 150 MHz. The circuit draws 395 mW from a 3.3-V supply and occupies an area of 1.2×1.5 mm²     

An 80-MHz 8-bit CMOS D/A converter

A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.     

A 5-MHz IF digital FM demodulator

Key requirements for digital frequency-modulation (FM) demodulators are wide spurious-free dynamic range in the intermediate-frequency quantizer, linear-phase passband filtering, and accurate frequency discrimination. The proposed FM demodulator implemented digitally achieves high linearity by numerical differentiation performed at a 112× oversampling rate, suppresses adjacent channels by placing zeros of the SINC function on them, and rejects amplitude-modulation (AM) components by numerical division. A 5-MHz FM demodulator integrated with a fourth-order bandpass delta-sigma front end exhibits 74.7 dB signal-to-noise ratio, -80.7 dB total harmonic distortion, and 61 dB AM rejection within a 9-kHz message bandwidth. The 0.65-μm CMOS chip occupies 3.5×3.5 mm² of active area and consumes 180 mW with 4-V supply when clocked at 20 MHz     

An integrated silicon bipolar receiver subsystem for 900-MHz ISMband applications

A wide-band dual conversion receiver subsystem is presented which is suitable for 900-MHz portable wireless applications including cordless telephony. The circuit features 118 dB of dynamic range and is operable from 6.5 V down through 2.7 V while consuming 26 mA. The receiver utilizes the MOSAIC V radio frequency (RF) silicon bipolar process and features an LNA, two mixers, two oscillators, second LO amplifier, dual modulus prescaler, LF amplifier, RSSI, coilless demodulator, and power down control     

A 160-MHz bipolar wide-band IF amplifier

Wide-band intermediate-frequency (IF) amplifiers are needed when the data rates of communication systems increase. A single wide-band IF amplifier can also be used for a radio band with several narrow-band channels of varying strengths. High linearity is then required if intermodulation products are not to disturb weak channels. We have previously reported a highly linear wide-band IF amplifier in a complementary metal-oxide-semiconductor process. Using a similar topology, an npn-only bipolar amplifier with even higher linearity is now presented. The amplifier is fully differential and operates with a 5 V supply, At 20 MHz, 5 V_pp over a 1 kΩ load, the measured total harmonic distortion is just 9.068%     

DRM/DAB数字广播无线接收机中高线性电流模第二中频CMOS混频器设计

本文提出了一种用于DRM/ DAB接收机第二中频下变频中的无源开关混频器。该电路由一个输入跨导级,无源电流开关级和电流放大器级构成。输入跨导级采用基于电阻并联反馈自偏置的电流复用技术以提高跨导和输出电阻。开关级引入动态偏置技术以保证开关管过驱动电压随工艺变化的稳定性。电流放大器基于低电压的第二代全平衡多输出电流转换器（FBMOCCII）,引入电流并联负反馈,可提供非常低的输入阻抗及高输出阻抗。设计采用中芯国际0.18微米RF CMOS工艺进行了验证。测试结果表明,该芯片电压增益是1.407dB,噪声指数NF是16.22dB,IIP3为4.5dBm。在1.8V的电源电压下,功耗为9.30mW。该设计体现了增益,噪声和线性度之间的良好折衷,其适合应用在DRM/ DAB无线接收机中的第二中频混频器中。     

An 8-MHz CMOS subranging 8-bit A/D converter

A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.     

A 100-MHz pipelined CMOS comparator

The authors describe the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8-bits, offset cancellation is incorporated in the first sense amplifier. The comparator has been integrated in a 2-μm CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate     

A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-/spl mu/m CMOS technology

A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62/spl deg/, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-/spl mu/m CMOS technology. The OTA's current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass /spl Sigma//spl Delta/ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a /spl plusmn/1.25-V supply.     

70-MHz IF 10-MHz bandwidth bandpass \Upsigma\Updelta modulator for WCDMA applications

A MASH bandpass $\Upsigma\Updelta$ modulator for wide-band code division multiple access (WCDMA) applications is presented. The signal bandwidth of the proposed modulator is 10?MHz centered around an intermediate frequency (IF) of 70.5?MHz. Two two-path second-order bandpass $\Upsigma\Updelta$ modulators make the MASH architecture, which realizes a noise transfer function with four couples of complex conjugate zeros. The proposed circuit, fabricated with a 0.18???m CMOS technology, uses a sampling frequency of 180?MHz to obtain a resolution of about 12?bits in the 10?MHz bandwidth around the IF. The measured modulator power consumption is 95?mW with a supply voltage of 1.8?V. The achieved figure-of-merit (FoM _BP ) is 0.37?pJ/conversion-level.     

MSK扩频接收机中放系统设计

本文提出了采用MSK信号格式的 3种扩频接收机中放系统模型 ,并用计算机模拟的方法分析比较了几种典型的干扰环境下 3种系统的性能 ,文中给出的曲线可供设计MSK扩频通信系统参考。     

A 12-Bit 200-MHz CMOS ADC

A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2 V supply.