Buffer allocation for real-time streaming applications running on heterogeneous multi-processors without back-pressure

The goal of buffer allocation for real-time streaming applications is to minimize total memory consumption, while reserving sufficient space for each data production, without overwriting any live data and guaranteeing the satisfaction of real-time constraints. Previous research has mostly focused on buffer allocation for systems with back-pressure. This paper addresses the problem of buffer allocation for systems without back-pressure. Since systems without back-pressure lack blocking behavior at the side of the producer, buffer allocation requires both best- and worst-case timing analysis.Our contributions are (1) extension of the available dataflow techniques with best-case analysis; (2) the closest common dominator-based and closest common predecessor-based lifetime analysis techniques; (3) techniques to model the initialization behavior and enable token reuse.Our benchmark set includes an MP3 decoder, a WLAN receiver, an LTE receiver and an LTE-Advanced receiver. We consider two key features of LTE-Advanced: (1) carrier aggregation and (2) EPDCCH processing. Through our experiments, we demonstrate that our techniques are effective in handling the complexities of real-world applications. For the LTE-Advanced receiver case study, our techniques enable us to compare buffer allocation required for different scheduling policies with effective impact on architectural decisions. A key insight in this comparison is that our improved techniques show a different scheduling policy to be superior in terms of buffer sizes compared to our previous technique. This dramatically changes the trade-off among different scheduling policies for LTE-Advanced receiver.     

Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC

Embedded systems often contain multiple applications, some of which have real-time requirements and whose performance must be guaranteed. To efficiently execute applications, modern embedded systems contain Globally Asynchronous Locally Synchronous (GALS) processors, network on chip, DRAM and SRAM memories, and system software, e.g. microkernel and communication libraries. In this paper we describe a dataflow formalisation to independently model real-time applications executing on the CompSOC platform, including new models of the entire software stack. We compare the guaranteed application throughput as computed by our tool flow to the throughput measured on an FPGA implementation of the platform, for both synthetic and real H.263 applications. The dataflow formalisation is composable (i.e. independent for each real-time application), conservative, models the impact of GALS on performance, and correctly predicts trends, such as application speed-up when mapping an application to more processors.     

Voltage island based heterogeneous NoC design through constraint programming

This paper discusses heterogeneous Network-on-Chip (NoC) design from a Constraint Programming (CP) perspective and extends the formulation to solving Voltage-Frequency Island (VFI) problem. In general, VFI is a superior design alternative in terms of thermal constraints, power consumption as well as performance considerations. Given a Communication Task Graph (CTG) and subsequent task assignments for cores, cores are allocated to the best possible places on the chip in the first stage to minimize the overall communication cost among cores. We then solve the application scheduling problem to determine the optimum core types from a list of technological alternatives and to minimize the makespan. Moreover, an elegant CP model is proposed to solve VFI problem by mapping and grouping cores at the same time with scheduling the computation tasks as a limited capacity resource allocation model. The paper reports results based on real benchmark datasets from the literature.     

Maximum-throughput mapping of SDFGs on multi-core SoC platforms

Data-Flow models are attracting renewed attention because they lend themselves to efficient mapping on multi-core architectures. The key problem of finding a maximum-throughput allocation and scheduling of Synchronous Data-Flow graphs (SDFGs) onto a multi-core architecture is NP-hard and has been traditionally solved by means of heuristic (incomplete) algorithms with no guarantee of global optimality. In this paper we propose an exact (complete) algorithm for the computation of a maximum-throughput mapping of applications specified as SDFG onto multi-core architectures. This is, to the best of our knowledge, the first complete algorithm for generic SDF graphs, including those with loops and a finite iteration bound. Our approach is based on Constraint Programming, it guarantees optimality and can handle realistic instances in terms of size and complexity. Extensive experiments on a large number of SDFGs demonstrate that our approach is effective and robust.     

Mapping workflow applications with types on heterogeneous specialized platforms

In this paper, we study the problem of optimizing the throughput of coarse-grain workflow applications, for which each task of the workflow is of a given type, and subject to failures. The goal is to map such an application onto a heterogeneous specialized platform, which consists of a set of processors that can be specialized to process one type of tasks. The objective function is to maximize the throughput of the workflow, i.e., the rate at which the data sets can enter the system. If there is exactly one task per processor in the mapping, then we prove that the optimal solution can be computed in polynomial time. However, the problem becomes NP-hard if several tasks can be assigned to the same processor. Several polynomial time heuristics are presented for the most realistic specialized setting, in which tasks of the same type can be mapped onto the same processor, but a processor cannot process two tasks of different types. Also, we give an integer linear program formulation of this problem, which allows us to find the optimal solution (in exponential time) for small problem instances. Experimental results show that the best heuristics obtain a good throughput, much better than the throughput obtained with a random mapping. Moreover, we obtain a throughput close to the optimal solution in the particular cases on which the optimal throughput can be computed (small problem instances or particular mappings).     

Synchronised execution on shared memory multiprocessors

Threads provides a mechanism for simulating the execution of parallel algorithms on a simplified model of a shared-memory multiprocessor. The algorithms can be expressed in a high-level block-structured language, which supports multiple threads of execution within a common body of program code. Results show an ability to achieve good speedup for small problems using algorithms derived by simple modifications of sequential algorithms. As well, a sibling thread synchronisation feature provides the basis for the synchronous execution of threads. k-parallel algorithms tailored to the machine size and implemented as synchronously executing iterations, can provide near linear speedup as the problem size is increased. The techniques described in this paper seem to promise an effective synchronous execution mode for shared-memory MIMD architectures.     

Supporting soft real-time parallel applications on multiprocessors

The prevalence of multicore processors has resulted in the wider applicability of parallel programming models such as OpenMP and MapReduce. A common goal of running parallel applications implemented under such models is to guarantee bounded response times while maximizing system utilization. Unfortunately, little previous work has been done that can provide such performance guarantees. In this paper, this problem is addressed by applying soft real-time scheduling analysis techniques. Analysis and conditions are presented for guaranteeing bounded response times for parallel applications under global EDF multiprocessor scheduling.     

基于电压岛的能量和可靠性感知NoC映射

面向支持电压岛的NoC平台,定义了可靠性约束下的能量感知NoC映射问题,提出一种基于禁忌搜索的优化方法.设计了一种新的能效变化率驱动的启发式算法,嵌套于NoC设计空间的搜索过程中,在IP核映射解的基础上实现各电压岛的电压映射.实验结果表明,本文算法可显著降低NoC能耗,并高效地确保NoC通信的可靠性要求.     

Parallel Execution of Prolog on Shared-Memory Multiprocessors

Logic programs offer many opportunities for the exploitation of parallelism.But the parallel execution of a task incurs various overheads.This paper focuses on the issues relevant to parallelizing Prolog on shared-memory multiprocessors efficiently.     

Functional programming on a dataflow architecture: Applications in real-time image processing

This paper presents a dataflow functional computer (DFFC) developed at the Etablissement Technique Central de l'Armement (ETCA) and dedicated to real-time image processing. Two types of data-driven processing elements, dedicated respectively to low-level and mid-level processings are integrated in a regular 3D array. The design of the DFFC relies on a close integration of the dataflow-architecture principles and the functional programming concept. An image processing algorithm, expressed with a syntax similar to that of functional programming (FP) is first converted into a dataflow graph. The nodes of this graph are real-time operators that can be implemented on the physical processors of the dataflow machine. This dataflow graph is then mapped directly onto the processor array. The programming environment includes a complete compilation stream from the FP specification to hardware implementation, along with a global operator database. Apart from being a research tool for real-time image processing, the DFFC may also be used to perform the automatic synthesis of autonomous vision automata from a high-level functional specification. An experimental system, including 1024 lowlevel custom dataflow processors and 12 T800 transputers, was built and can perform up to 50 billion operations/s. Several image processing algorithms were implemented on this system and run in real-time at digital video speed.     

基于Web的XML与数据库映射

本文讨论了XML与数据之间的结构对比，并介绍了基于Web方式下的XML与数据库之间映射的实例。     

Preemptive open shop scheduling with multiprocessors: polynomial cases and applications

This paper addresses a multiprocessor generalization of the preemptive open-shop scheduling problem. The set of processors is partitioned into two groups and the operations of the jobs may require either single processors in either group or simultaneously all processors from the same group. We consider two variants depending on whether preemptions are allowed at any fractional time points or only at integer time points. We reduce the former problem to solving a linear program in strongly polynomial time, while a restricted version of the second problem is solved by rounding techniques. Applications to course scheduling and hypergraph edge coloring are also discussed.     

基于模式映射的查询计划生成算法

因特网的迅速发展使得多数据源综合集成日益重要.但是,不同数据源之间数据结构和语义的异构性导致数据集成是相当困难的.本文提出了一种基于模式映射的查询计划生成算法.该算法在正确定义映射规则的前提下,根据不同的查询条件和不同的数据源模式,自动构造查询计划,并保证结果数据满足目标模式结构与引用完整性要求.     

基于混沌映射的图像置乱算法

混沌映射具有对初始条件的敏感性、良好的随机性、相关性和复杂性等特性.基于此提出了一种快速、安全的图像混沌置乱算法,实验表明,该算法达到了很好的效果.尤其在大型图像数据库的应用中,该算法在保证安全性的前提下,能在极短的时间内对大量图像进行置乱与恢复.     

基于三角剖分的人脸纹理映射

采用通用的三维人脸模型和任意的人脸纹理图像,基于Delaunay三角剖分,提出了一种灵活的3D人脸的纹理映射方法。该方法对人脸特征点集做三角剖分,在纹理图像和三维网格之间建立了一个准确的拓扑同构映射关系,从而得到高真实度的纹理映射。该算法不受网格调整精度的影响,同时适用于不同的纹理映射到同一三维人脸模型上。     

保证QoS的片上网络低能耗映射与路由方法

为解决二维mesh片上网络的服务质量和低能耗问题,提出基于最优化搜索的拓扑映射与路由方法Q-LEMR．该方法以降低芯片通信能耗为目标,在保证系统延迟与带宽的服务质量的前提下,自动将给定应用的IP核映射到片上网络结构上,并为通信踪迹定制设计确定的、非死锁的最短路径路由;同时通过加速策略使映射和路由的计算在可接受的时间范围内完成．实验结果表明,Q—LEMR较现有工作平均降低通信能耗28．8％,并满足服务质量要求．     

对等数据管理系统中数据映射推导问题的研究

映射表是对等数据管理系统广泛使用的一种数据映射工具。通过构造大量新的映射关系,映射推导技术能极大地提高数据共享程度。已有的映射推导研究集中于理论分析,该文在探讨映射推导问题的基础上,从用户角度出发设计了一个映射关系模型,在此基础上,给出了数据映射推导系统的总体框架。     

Constraint satisfaction with an object-oriented knowledge representation language

This article gives a detailed presentation of constraint satisfaction in the hybrid LAURE language. LAURE is an object-oriented language for Artificial Intelligence (AI) applications that allows the user to combine rules, constraints, and methods that cooperate on the same objects in the same program. We illustrate why this extensibility is necessary to solve some large and difficult problems by presenting a real-life application of LAURE. We describe the syntax and the various modes in which constraints may be used, as well as the tools that are proposed by LAURE to extend constraint resolution. The resolution strategy as well as some implementation details are given to explain how we obtain good performances.     

本体映射概念及方法的研究

本体映射是本体集成的一个关键环节.构建本体映射是分布式环境下实现不同本体之间共享和交流的基础性工作.本文首先通过举例分析了本体映射的概念,再从映射的构建思路和具体实现的角度对本体映射的方法进行了总结,最后分析了现在本体映射存在的问题和可能的研究前景.