基于FPGA的16位数据路径的AES IP核

提出一种基于FPGA的16位数据路径的高级加密标准AES IP核设计方案。该方案采用有限状态机实现,支持密钥扩展、加密和解密。密钥扩展采用非并行密钥扩展,减少了硬件资源的占用。该方案在Cyclone II FPGA芯片EP2C35F484上实现,占用20 070个逻辑单元（少于60%的资源）,系统最高时钟达到100 MHz。与传统的128位数据路径设计相比,更方便与处理器进行接口。     

Integrating External and Internal Clock Synchronization

We address the problem of how to integrate fault-tolerant external and internal clock synchronization. In this paper we propose a new external/internal clock synchronization algorithm which provides both external and internal clock synchronization for as long as a majority of the reference time servers (servers with access to reference time) stay correct. When half or more of the reference time servers are faulty, the algorithm degrades to a fault-tolerant internal clock synchronization algorithm. We prove that at least 2 F+1 reference time servers are necessary for achieving external clock synchronization when up to F reference time servers can suffer arbitrary failures, thus the proposed algorithm provides maximum fault-tolerance. In this paper we also derive lower bounds for the best maximum external deviation achievable in standard mode and the best drift rate achievable in degraded mode. Our algorithm is optimal with respect to these two bounds: (1) the maximum external deviation is optimal in standard mode, and (2) the drift rate of the clocks is optimal in standard and degraded mode.     

Gradient clock synchronization

We introduce the distributed gradientclock synchronization problem. As in traditional distributed clock synchronization, we consider a network of nodes equipped with hardware clocks with bounded drift. Nodes compute logical clock values based on their hardware clocks and message exchanges, and the goal is to synchronize the nodes' logical clocks as closely as possible, while satisfying certain validity conditions. The new feature of gradient clock synchronization GCS for short) is to require that the skew between any two nodesy' logical clocks be bounded by a nondecreasing function of the uncertainty in message delay (call this the distance) between the two nodes, and other network parameters. That is, we require nearby nodes to be closely synchronized, and allow faraway nodes to be more loosely synchronized. We contrast GCS with traditional clock synchronization, and discuss several practical motivations for GCS, mostly arising in sensor and ad-hoc networks. Our main result is that the worst case clock skew between two nodes at distance d or less from each other is Ω(d + , where D is the diameter of the network. This means that clock synchronization is not a localproperty, in the sense that the clock skew between two nodes depends not only on the distance between the nodes, but also on the size of the network. Our lower bound implies, for example, that the TDMA protocol with a fixed slot granularity will fail as the network grows, even if the maximum degree of each node stays constant.     

应用于片上系统中低功耗IP核设计的自适应门控时钟技术

门控时钟技术一直以来是降低芯片动态功耗的有效方法.文章结合片上系统(SoC)的结构特性和设计特点,分析已有的各种门控时钟技术的优缺点,指出这些缺点是SoC设计中的严重障碍,随后抽象出IP核工作模型,提出了仅用非常简单的逻辑就可以方便应用于IP核的自适应门控时钟技术.这种技术在不影响性能的前提下,可以根据IP核的应用状况自动开关时钟,不但可以降低动态功耗,还可以结合门控电源技术降低漏电功耗.对一款真实SoC中浮点IP核的改造实验表明,在不降低性能的前提下,可以平均降低62.2%的动态功耗,同时理论上平均降低70.9%的漏电功耗.     

A predictive synchronizer for periodic clock domains

An adaptive predictive clock synchronizer for systems on chip incorporating multiple clock domains is presented. The synchronizer takes advantage of the periodic nature of clocks in order to predict potential conflicts in advance, and to conditionally employ an input sampling delay to avoid such conflicts. The result is conflict-free synchronization with maximal throughput and minimal latency. The adaptive predictive synchronizer adjusts automatically to a wide range of clock frequencies, regardless of whether the transmitter is faster or slower than the receiver. The synchronizer also avoids sampling duplicate data or missing any input. A novel method is presented for formal treatment of synchronizers and metastability. Correct operation of the synchronizer is formally proven and verified.     

Design and verification of an efficient WISHBONE-based network interface for network on chip

In this paper, a generic asynchronous First In First Out (FIFO) based WISHBONE compatible plug and play Network Interface (NI) for Network on Chip (NoC) is designed and verified. Four different types of encoded asynchronous FIFOs namely binary, Gray, one-hot and Johnson are designed and analyzed. It is found that Gray-code asynchronous FIFO is the best to handle the asynchronous clock domain issues in NI. The control signals of the WISHBONE bus wrappers from/to asynchronous FIFOs and packing/unpacking modules are asserted concurrently at the same rising edge of the respective router and IP clocks to reduce the latency. The same NI has been utilized for transferring data between synchronous as well as asynchronous clock domains irrespective of clock frequency and phase differences. The proposed NI ensures the seamless high data throughput between the routers and IP cores with minimal latency, higher throughput, higher speed and utilized lesser area compared to the existing design.     

异步环境中基于时钟精度差的时钟同步

在异步通信模型的基础上，提出了一个基于时钟精度差的时钟同步策略，并给出了一个完整的系统模型，研究的重点有3个方面：（1）在时钟同步过程中使用单向信息传输策略，可以有效地减少网络负载；（2）客户机使用本地节点的时间信息和来自于参考时钟的时间戳信息构造一个线性数学模型，并获得本地时钟与参考时钟的运行精度差；（3）根据本地节点计算出的时钟精度差，构造一个自适应的容错模型，能够保证当本地节点与参考节点的连接出现故障时，本地的时钟同步系统还能够正常工作。该文不仅给出了一个详细的数学模型，而且还在实际的Internet环境中进行了模拟试验，取得了满意的结论。     

IEEE1588精准时钟协议的IP设计

IEEE1588协议是一种应用于分布式测量和控制系统中的精准时钟协议,文章提出IEEE1588协议IP实现的设计架构,并详述了架构中最佳主时钟（BMC）以及时钟校准电路的设计原理和实现。通过模型仿真验证了该设计的正确性。     

基于MIPS核的片上系统总线控制器设计

针对基于MIPS核的高清晰度电视(HDTV)的片上系统,设计了一种EC总线控制器。在MIPS核外采用高速缓存来提高总线效率。实现了流水线总线事件,解决了EC总线时钟与外设时钟的转换。通过MIPS总线功能模块(BFM)的时序仿真验证了该控制器的正确性。0.25-μmCMOS工艺综合了EC总线控制器的RTL代码,总线时钟可达到149MHz。最后通过了FPGA验证。     

Dynamic FTSS in asynchronous systems: The case of unison

Distributed fault-tolerance can mask the effect of a limited number of permanent faults, while self-stabilization provides forward recovery after an arbitrary number of transient faults hit the system. FTSS (Fault-Tolerant Self-Stabilizing) protocols combine the best of both worlds since they tolerate simultaneously transient and (permanent) crash faults. To date, deterministic FTSS solutions either consider static (i.e. fixed point) tasks, or assume synchronous scheduling of the system components.In this paper, we present the first study of deterministic FTSS solutions for dynamic tasks in asynchronous systems, considering the unison problem as a benchmark. Unison can be seen as a local clock synchronization problem as neighbors must maintain digital clocks at most one time unit away from each other, and increment their own clock value infinitely often. We present several impossibility results for this difficult problem and propose an FTSS solution (when the problem is solvable) for the state model that exhibits optimal fault-containment.     

基于双端口RNI的容错NoC架构

为解决片上网络中故障路由器与IP核的通信问题,设计一种低硬件开销的双端口资源网络接口,在传统2D-mesh结构基础上,通过添加部分链路,将每个IP核连接到2个路由器上,并针对该架构设计相应的容错路由算法。实验结果表明,该方案硬件开销较小、容错能力较强。     

高性能众核处理器芯片时钟网络设计

随着芯片工艺演进与设计规模增加,高性能众核处理器芯片时钟网络设计面临时序和功耗的全方位挑战。为降低芯片时钟网络功耗并缓解时钟网络分布受片上偏差影响导致的时钟偏斜,在H-Tree+MESH混合时钟网络结构的基础上,结合新一代众核处理器芯片面积大及核心时钟网络分布广的特点,基于标准多源时钟树设计策略构建多源时钟树综合（MRCTS）结构,通过全局H-Tree时钟树保证芯片不同区域间时钟偏斜的稳定可控,利用局部时钟树综合进行关键路径的时序优化以实现时序收敛。实验结果表明,MRCTS能在保证时钟延时、时钟偏斜等性能参数可控的基础上,有效降低时钟网络的负载和功耗,大幅压缩综合子模块的布线资源,加速关键路径的时序收敛,并且在相同电源电压和时钟频率的实测条件下,可获得约22.15%的时钟网络功耗优化。     

PTP网络非对称时延抖动修正算法设计与分析

为了改进PTPV2时间同步网络非对称时延抖动对主从时钟同步精度的影响,设计了传输报文的非对称时延抖动修正算法。基本思路是在主从时钟交换报文信息中,找出最佳报文用于从时钟的调整。采用两级过滤先进增强时间恢复算法,即使发生网络传输阻塞,也能筛选出未受阻塞的幸运报文用于时钟偏差估计。新算法能够很容易集成到PTPV2协议中,而不会影响基本的报文信息交换。实际测试结果表明,新设计的时间恢复算法,在普通交换机网络中,可有效抑制非对称时延抖动,主从时钟同步精度也可优于100ns。     

一种宽带高性能TIADC时钟发生器

针对并行交替模拟数字转换器(TIADC)发展遇到的时钟瓶颈,提出了一种宽带高性能TIADC时钟发生器设计方案.该方案利用时钟分路器和可编程延迟器分别实现通道扩展和相位延迟,采用可配置时钟源和逻辑转换电路使时钟发生器能够输出低抖动的CMOS和ECL逻辑TIADC时钟.设计实现的时钟发生嚣已经成功用于4通道12 bit 320 MHz采样率的TIADC系统.测试结果表明,该时钟发生器具有10 ps延迟偏差和在80MHz频率下不超过2 ps的时钟抖动.     

基于RTEthernet改进的时钟同步算法

以太网其庞大的网络系统在复杂的环境中存在网络链路延迟,节点时钟的漂移,同步能力差等问题。通过研究RTEthernet协议的起源和工作原理,考虑到影响实时以太网时间同步精密度的时钟拜占庭故障、网络传输延迟和漂移率等三个因素,建立了符合RTEthernet协议的通信模型。对FTA时钟同步算法在故障下时钟同步精密度损失率提升较少的问题进行了研究,引入了滑动窗口技术,提出了容错滑动窗口（Fault-Tolerant Sliding Window, FTSW）算法。容错滑动窗口算法能进一步提高分布式系统在进行时钟同步是对故障节点的容错能力。最后,使用CANoe仿真工具对FTSW算法进行仿真验证, FTSW算法的容错性优于FTA时钟同步算法算法,且在系统（七个节点）中存在两个拜占庭故障的情况下,同步后的精密度损失率降低了7.1%。     

Measuring jitter and phase error in microprocessor phase-lockedloops

The use of phase-locked loops (PLLs) for clock generation in modern microprocessors has been proliferating in recent years. This is because PLLs have the advantages of allowing multiplication of the reference clock frequency and allowing phase alignment between chips. The PLL locks to a reference clock but can generate output clocks that are a multiple of the reference. It is argued that excessive “jitter”, caused primarily by power supply noise, can detract from the advantages of phase-locked loops. Moreover, in a multichip system, the accumulated phase error must be measured-not just the jitter     

Real-time system = discrete system + clock variables

This paper introduces, gently but rigorously, the clock approach to real-time programming. We present with mathematical precision, assuming no prerequisites other than familiarity with logical and programming notations, the concepts that are necessary for understanding, writing, and executing clock programs. In keeping with an expository style, all references are clustered in bibliographic remarks at the end of each section. The first appendix presents proof rules for verifying temporal properties of clock programs. The second appendix points to selected literature on formal methods and tools for programming with clocks. In particular, the timed automaton, which is a finite-state machine equipped with clocks, has become a standard paradigm for real-time model checking; it underlies the tools HyTech, Kronos, and Uppaal, which are discussed elsewhere in this volume.     

基于分布式系统实现时钟同步的统计平均算法

讨论了分布式系统中时钟同步的系统模型,远端时钟读取方法以及双向通信传输过程,给出了3种不同的时钟同步方案,同时,对基于多次同步消息的冗余传输,提出了新的基于统计平均的时钟同步算法。通过多步时间传输协议,在较短同步周期内对时钟进行同步。     

热安全约束下异构多核系统动态映射方法

异构多核平台通过集成不同类型的处理核来为系统设计提供灵活性,从而使应用程序可以根据自身需求动态地选择不同类型的处理核来进行处理,实现应用程序的高效运行。随着半导体技术的发展,单芯片上集成的核心数量随之增加,使得现代多核处理器具有更高的功率密度,而这会导致芯片温度的升高,最终会对系统性能造成一定的负面影响。为了充分发挥出异构多核处理系统的性能优势,提出一种在满足温度安全功率的前提下,以最大化系统性能为目标的动态映射方法。该方法考虑异构多核系统的两种异构指标来确定映射方案：第一种异构指标是核心类型,不同类型的处理核具有不同的特征,因而它们适用于处理不同的应用程序;第二种异构指标是热感受性,芯片上不同的处理核位置具有不同的热感受性,越是中心位置的处理核受到的来自于其他处理核的热传递越多,因而温度也就越高。为此,提出一种基于神经网络性能预测器来对线程与处理核类型进行匹配,并利用热安全功率（TSP）模型将经过匹配后的线程映射到芯片上的具体位置。实验结果表明,所提出的方法与常见的轮询调度（RRS）相比,能在保证热安全约束的前提下将平均每个时钟周期内程序所执行的指令数,即指令/周期（IPC）提高53%左右。     

一种节能型可升级异步FIFO的FPGA实现

提出了一种节能并可升级的异步FIFO的FPGA实现。此系统结构利用FPGA内自身的资源控制时钟的暂停与恢复,实现了高能效、高工作频率的数据传输。该系统在Xilinx的VC4VSX55芯片中实现,实际可工作于高达100/153.6MHz的读/写时钟域。本文所提出的结构不依赖于现有的IP核,基于此结构易建立可升级的IP核。