A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation

We present ultra-low-voltage circuit design techniques for a fractional-N RF synthesizer with two-point modulation which was realized in 90-nm CMOS using only regular ${rm V}_{rm T}$ devices.; the voltage controlled oscillator, phase-frequency detector and charge pump operate from a 0.5 $~$V supply while the divider uses a 0.65$~$V supply. The frequency synthesizer achieves a phase noise better than $-$120 dBc/Hz at 3 MHz, while consuming 6 mW. A calibration technique to equalize the gain between the two modulation ports is introduced and enables phase/frequency modulation beyond the loop bandwidth of the phase-locked loop. Measurement results for 2-Mb/s GFSK modulation are presented.      

A 0.22 V Quadrature VCO in 90 nm CMOS Process

This letter presents an ultra-low voltage quadrature voltage-controlled oscillator (QVCO). The LC-tank QVCO consists of two low-voltage voltage-controlled oscillators (VCOs) with the body dc biased at the drain bias through a resistor. The superharmonic and back-gate coupling techniques are used to couple two differential VCOs to run in quadrature. The proposed CMOS QVCO has been implemented with the UMC 90 nm CMOS technology and the die area is 0.827 $, times ,$0.913 mm $^{2}$. At the supply voltage of 0.22 V, the total power consumption is 0.33 mW. The free-running frequency of the QVCO is tunable from 3.42 to 3.60 GHz as the tuning voltage is varied from 0.0 to 0.3 V. The measured phase noise at 1 MHz offset is ${-}112.97$ dBc/Hz at the oscillation frequency of 3.55 GHz and the figure of merit (FOM) of the proposed QVCO is about ${-}188.79$ dBc/Hz.      

A Dual-Band Self-Oscillating Mixer for -Band and -Band Applications

A self-oscillating mixer that employs both the fundamental and harmonic signals generated by the oscillator subcircuit in the mixing process is experimentally demonstrated. The resulting circuit is a dual-band down-converting mixer that can operate in $C$ -band from 5.0 to 6.0 GHz, or in $X$-band from 9.8 to 11.8 GHz. The oscillator uses active superharmonic coupling to enforce the quadrature relationship of the fundamental outputs. Either the fundamental outputs of the oscillator or the second harmonic oscillator output signals that exists at the common-mode nodes are connected to the mixer via a set of complementary switches. The mixer achieves a conversion gain between 5–12 dB in both frequency bands. The output 1-dB compression points for both modes of the mixer are approximately $-{hbox{5 dBm}}$ and the output third-order intercept point for $C$ -band and $X$ -band operation are 12 and 13 dBm, respectively. The integrated circuit was fabricated in 0.13-$mu {hbox{m}}$ CMOS technology and measures ${hbox{0.525 mm}}^{2}$ including bonding pads.      

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 $mu{hbox{s}}$. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under $-$ 75 dBc. The phase noise at 400 kHz and 3 MHz are $-$115.6 dBc/Hz and $-$134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 $mu$ m CMOS process, and occupies an active area of 0.85 ${hbox{mm}}^{2}$ and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.      

A Wide Tuning Range 69 GHz Push-Push VCO Using 0.18 CMOS Technology

A wide tuning range V-band push-push CMOS voltage controlled oscillator (VCO) is proposed in this study. A new core complementary Colpitts structure was adopted in a 0.18 $mu{rm m}$ CMOS process to reduce dc power consumption and to improve tuning range owing to the reduction weighting of FET induced capacitance of L-C tank. The designed VCO oscillates from 64.2 to 69.4 GHz with a 5.2 GHz tuning range under a control voltage range of 1.2 V. The measured phase noise at 1 MHz offset is $-76.23~ {rm dBc}/{rm Hz}$ at 69.39 GHz. The power consumption of the VCO core is only 27.52 mW.      

A K-Band CMOS Quadrature Frequency Tripler Using Sub-Harmonic Mixer

A low-power frequency tripler is designed by using the sub-harmonic mixer configuration for K-band applications. The proposed circuit features quadrature signal generation, applicable to LO signal synthesis in millimeter-wave wireless transceivers. It achieves conversion gain of $-$5.7 dB at the output frequency of 21 GHz. Implemented in a 0.18 $mu{rm m}$ CMOS technology, the circuit consumes power of 7.5 mW with 1.5 V supply voltage. The entire die occupies an area of $1000times 1050 mu{rm m}^{2}$.      

A 1.94 to 2.55 GHz, 3.6 to 4.77 GHz Tunable CMOS VCO Based on Double-Tuned, Double-Driven Coupled Resonators

This paper presents a multi-band CMOS VCO using a double-tuned, current-driven transformer load. The dual frequency range oscillator is based on enabling/disabling the driving current in the secondary port of the transformer. This approach eliminates the effect of switches connected directly to the VCO tank whose capacitance and on-resistance affect both the tuning range and the phase noise of a typical multi-band oscillator. The relation between the coupling coefficient of the transformer load, selection of frequency bands, and the resulting quality factor at each band is investigated. The concept is validated through measurement results from a prototype fabricated in 0.25 $~muhbox{m}$ CMOS technology. The VCO has a measured tuning range of 1.94 to 2.55 GHz for the low frequency range and 3.6 to 4.77 GHz for the high frequency range. It draws a current of 1 mA from 1.8 V supply with a measured phase noise of $-hbox{116~dBc/Hz}$ at 1 MHz offset from a 2.55$~$GHz carrier. For the high frequency band, the VCO draws 10.1 mA from the same supply with a phase noise of $-hbox{122.8~dBc/Hz}$ at 1$~$ MHz offset from a 4.77 GHz carrier.      

A Fully-Differential Complementary Hartley VCO in 0.18 m CMOS Technology

In this letter, a new complementary Hartley (C-Hartley) voltage controlled oscillator (VCO) with fully differential outputs is proposed, in which the self-biasing configuration is introduced to solve the biasing difficulty of a Hartley VCO by employing a five-port transformer. The proposed C-Hartley VCO with the center frequency of 5.6 GHz is implemented in a 1P6M 0.18 $mu$m CMOS process. The measurement result shows that the phase noise is ${-}123.6$ dBc/Hz at 1 MHz offset frequency, while dissipating 6.5 mA from 1.6 V supply with the FOM of ${-}188.5$ dBc.      

A 36–80 GHz High Gain Millimeter-Wave Double-Balanced Active Frequency Doubler in SiGe BiCMOS

This letter presents a high conversion gain double-balanced active frequency doubler operating from 36 to 80 GHz. The circuit was fabricated in a 200 GHz ${rm f}_{rm T}$ and ${rm f}_{max}$ 0.18 $mu$m SiGe BiCMOS process. The frequency doubler achieves a peak conversion gain of 10.2 dB at 66 GHz. The maximum output power is 1.7 dBm at 66 GHz and ${-}3.9$ dBm at 80 GHz. The maximum fundamental suppression of 36 dB is observed at 60 GHz and is better than 20 dB from 36 to 80 GHz. The frequency doubler draws 41.6 mA from a nominal 3.3 V supply. The chip area of the active frequency doubler is 640 $mu$m $,times,$424 $mu$m (0.272 mm $^{2}$) including the pads. To the best of authors' knowledge, this active frequency doubler has demonstrated the highest operating frequency with highest conversion gain and output power among all other silicon-based active frequency doublers reported to date.      

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.      

125-GHz Diode Frequency Doubler in 0.13-$mu{hbox {m}}$ CMOS

The first mm-wave Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler built in 130-nm CMOS uses a balanced topology with two shunt Schottky barrier diodes, and exhibits $sim$10-dB conversion loss as well as $-$1.5-dBm output power at 125 GHz. The input matching is better than $-$10$~$dB from 61 to 66 GHz. The rejection of fundamental signal at output is greater than 12 dB for input frequency from 61 to 66$~$GHz. The doubler can generate signals up to 140 GHz.      

A Dual-Band CMOS Voltage-Controlled Oscillator Implemented With Dual-Resonance LC Tank

A new fully integrated, dual-band CMOS voltage controlled oscillator (VCO) is presented. The VCO is composed of n-core cross-coupled Colpitts VCOs and was implemented in 0.18 $mu$m CMOS technology with 0.8 V supply voltage. The circuit allows the VCO to operate at two resonant frequencies with a common LC tank. The VCO has two control inputs, one for continuous control of the output frequency and one for band switching. This VCO is configured with 5 GHz and 12 GHz frequency bands with differential outputs. The dual-band VCO operates in 4.78–5.19 GHz and 12.19–12.61 GHz. The phase noises of the VCO operating at 5.11 and 12.2 GHz are ${-}117.16$ dBc/Hz and ${-}112.15$ dBc/Hz at 1 MHz offset, respectively, while the VCO draws 3.2/2.72 mA and 2.56/2.18 mW consumption at low/high frequency band from a 0.8 V supply.      

Adaptive On-Chip Power Supply With Robust One-Cycle Control Technique

In this paper, an integrated adaptive-output switching converter is proposed. The design employs a one-cycle control for fast line regulation and a single outer loop for tight load regulation and fine tuning. A switched-capacitor integrator is introduced to the one-cycle control to obtain positive integration with a single positive power supply, allowing a standard low-cost CMOS fabrication process. To improve the efficiency, a dynamic loss control technique is presented. The converter was designed and fabricated with 0.35 $mu{hbox{m}}$ N-well CMOS process. With a supply voltage of 3 V, a voltage ripple of less than $pm$20 mV is measured. The maximum efficiency is 92% with a load power of 475 mW. The converter exhibits a tracking speed of 23.75 $mu{hbox{s/V}}$ for both start-up and reference voltage transitions. The recovery time for a 20% load change is approximately 9.5 $mu{hbox{s}}$.      

A Differential Clapp-VCO in 0.13 $mu{rm m}$ CMOS Technology

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 $mu{rm m}$ CMOS 1P8M process. The designed circuit topology is an all nMOS LC-tank Clapp-VCO using a series-tuned resonator. At the supply voltage of 0.9 V, the output phase noise of the VCO is $-$110.5 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 18.78 GHz, and the figure of merit is $-$188.67 dBc/Hz. The core power consumption is 5.4 mW. Tuning range is about 3.43 GHz, from 18.79 to 22.22 GHz, while the control voltage was tuned from 0 to 1.3 V.      

Analysis and Design of a Wide-Tuning-Range VCO With Quadrature Outputs

A quadrature voltage-controlled oscillator (QVCO) with a wide tuning range is proposed and implemented in the TSMC 0.18- $mu{rm m}$ CMOS process. The said QVCO uses a cross-coupled structure and a current-reuse technology to produce the quadrature signal and to save power consumption and area, respectively. Based on our measurement, the phase noise with 1-MHz offset from the carrier frequency of 3.6 GHz is $-$ 114 dBc/Hz and the proposed QVCO has a wide-band tuning range of 3.6–4.9 GHz. Also, the maximal phase error and power imbalance are less than 5$^{circ}$ and 1.5 dB, respectively, and the power consumption is 8 mW at 2-V power supply voltage.      

Single- and Dual-Polarized Tunable Slot-Ring Antennas

Single- and dual-polarized slot-ring antennas with wideband tuning using varactor diodes have been demonstrated. The single-polarized antenna tunes from 0.95 to 1.8 GHz with better than ${-}13$ dB return loss. Both polarizations of the dual-polarized antenna tune from 0.93 to 1.6 GHz independently with better than ${-}10$ dB return loss and $> !20!$ dB port-to-port isolation over most of the tuning range. The capacitance of the varactor diodes varies from 0.45 to 2.5 pF, and the antennas are printed on 70 $,times,$70 $,times,$0.787 mm ${^3}$ substrates with ${epsilon_{rm r} = 2.2}$. The dual-polarized slot-ring antenna can either be made both frequency- and polarization-agile simultaneously, or can operate at two independent frequencies on two orthogonal polarizations. To our knowledge, this is the first dual-polarized tunable antenna with independent control of both polarizations over a 1.7:1 frequency range.      

Low Noise Wide Tuning Range Quadrature Ring Oscillator for Multi-Standard Transceiver

This letter presents a low phase noise quadrature ring oscillator with new start-up circuit. The oscillator architecture is a two-stage differential ring with an additional pair of transition-assistance transistors. The circuit was implemented in 0.18 $mu{rm m}$ CMOS technology and the measured tuning range of the prototype device is from 1.7 GHz to 5.5 GHz and figure of merit (FOM) is ${- 162}~{rm dB}$. The proposed area of application is the core of the local oscillator in a multi-standard wireless transceiver.      

Heterogeneous High-Performance Quantum-Cascade Laser Sources for Broad-Band Tuning

A heterogeneous high-performance quantum-cascade laser gain chip comprising two bound-to-continuum active region designs emitting at 8.2 and 9.3 $mu$m is presented. Its extrapolated gain spectrum has a full-width at half-maximum (FWHM) of 350 cm$^{ - 1}$. Though a broad gain bandwidth invariably results in a reduced gain cross section, devices with a high-reflection coated back facet still lase continuous-wave (CW) up to a temperature of 50 $^{circ}$C and demonstrates output powers in excess of 100 mW at 30$^{circ}$C. Such high performance was achieved by designing the waveguide in a buried heterostructure fashion and epi-down mounting on a diamond submount, resulting in a thermal resistance of only 4.8 K/W. In pulsed mode, we reached a peak output power of 1 W at room temperature. Finally, in order to prove the usability for broad-band tuning, this chip was antireflection coated on the front facet with a residual reflectivity of $≪ {hbox {2.5}} times {hbox {10}}^{-3}$ and used in our external cavity (EC) setup operated at room temperature. In pulsed mode, we were able to tune the gain chip over 292 cm $^{-1}$, which is 25% of center frequency. In CW, we reached a coarse tuning range of 201 cm$^{-1}$ (18%) and an output power in excess of 135 mW at the gain maximum at 15$^{circ}$C. This gain chip enabled CW room temperature EC tuning with output powers in excess of 20 mW over 172 cm 相似文献   

A 4.39–5.26 GHz LC-Tank CMOS Voltage-Controlled Oscillator With Small VCO-Gain Variation

A wide band CMOS LC-tank voltage controlled oscillator (VCO) with small VCO gain $(K_{VCO})$ variation was developed. For small $K_{VCO}$ variation, serial capacitor bank was added to the LC-tank with parallel capacitor array. Implemented in a 0.18 $mu{rm m}$ CMOS RF technology, the proposed VCO can be tuned from 4.39 GHz to 5.26 GHz with the VCO gain variation less than 9.56%. While consuming 3.5 mA from a 1.8 V supply, the VCO has $-$ 113.65 dBc/Hz phase noise at 1 MHz offset from the carrier.      

Low Phase Noise Differential Vackar VCO in 0.18 CMOS Technology

In this letter, we present the measured performance of a differential Vackar voltage-controlled oscillator (VCO) implemented for the first time in CMOS technology. The Vackar VCO provided good isolation between the LC tank and the loss-compensating active circuit; thus, excellent frequency stability was achieved over the frequency tuning range. The Vackar VCO was implemented using nMOS transistors and an LC tank in a 0.18 $mu{rm m}$ RF CMOS process. The oscillation frequency ranged from 4.85 to 4.93 GHz. The measured phase noise of the Vackar VCO at 1 MHz offset was $-124.9 ~{rm dB}/{rm Hz}$ at 4.9 GHz with a figure-of-merit (FOM) of $-188 ~{rm dBc}/{rm Hz}$.