Realistic end-to-end simulation of the optoelectronic links andcomparison with the electrical interconnections for system-on-chipapplications

A detailed comparison of optoelectronic versus electrical interconnections for system-on-chip applications is performed in terms of signal latency and power consumption. Realistic end-to-end models of both interconnection schemes are employed in order to evaluate critical performance parameters. A variety of electrical and optoelectronic interconnection configurations are implemented and simulated using accurate optical device and electronic circuit models integrated under an integrated circuit (IC) design computer-aided design tool. Two commercial complementary metal-oxide-semiconductor (CMOS) technologies (0.8 μm and 0.25 μm) are used for the estimation of the signal latency and the power consumption as a function of the interconnection length for the different link configurations. It was found that optoelectronic interconnects outperform their electrical counterparts, under certain conditions, especially for relatively long lines and multichannel data links     

Power minimization for dynamic PLAs

Dynamic programmable logic arrays (PLAs) which are built of the nor-nor structure, have been very popular in high performance design because of their high-speed and predictable routing delay. However, the nor-nor structure incurs high switching activity in product lines and, thus, results in large power consumption. In this paper, we propose a new dynamic PLA structure which incorporates super product lines. A super product line adds the nand functionality on top of the nor structure, thus, lowering the switching activities in the product lines, as well as power consumption. Since there are many candidates for super product lines, we have developed a computer-aided design (CAD) algorithm based on the maximum weighted matching to find the optimal solution. We have performed experiments on a large set of Microelectronics Center of North Carolina (MCNC) benchmark circuits. The post simulation results show significant reduction in power consumption. Among the experimental circuits, circuit alu3 has the highest power saving 62.9% with the delay overhead 5.4%, and circuit newpla2 has the lowest power saving with delay overhead 22.7%. In addition, circuit in4 improves the delay with 5.7%. On the average, the power consumption can be saved 55.8% and the delay overhead is merely 3.3% for 25 circuits.     

Power analysis and minimization techniques for embedded DSPsoftware

Power is becoming a critical constraint for designing embedded applications. Current power analysis techniques based on circuit-level or architectural-level simulation are either impractical or inaccurate to estimate the power cost for a given piece of application software. In this paper, an instruction-level power analysis model is developed for an embedded digital signal processor (DSP) based on physical current measurements. Significant points of difference have been observed between the software power model for this custom DSP processor and the power models that have been developed earlier for some general purpose commercial microprocessors. In particular, the effect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the processor has special architectural features that allow dual memory accesses and packing of instructions into pairs. The energy reduction possible through the use of these features is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A microarchitectural power model for the multiplier is developed and analyzed for further power minimization. In order to exploit all of the above effects, a scheduling technique based on the new instruction-level power model is proposed. Several example programs are provided to illustrate the effectiveness of this approach. Energy reductions varying from 26% to 73% have been observed. These energy savings are real and have been verified through physical measurement. It should be noted that the energy reduction essentially comes for free. It is obtained through software modification, and thus, entails no hardware overhead. In addition, there is no loss of performance since the running times of the modified programs either improve or remain unchanged     

光捕捉技术有望推进光电通信

普林斯顿大学的研究人员已经发现了制造准晶聚合物（quasicrystalline polymer）结构的方法，这代表了光子学潜在的重大进步。这种结构能够控制光的传播，使得光子通信系统成为可能。目前，在光子电路中，光不能进行锐角的转折，准晶点阵技术可使光在电路中传播时产生锐角转折，这将推动高速通信和计算设备的发展。     

Novel flip-chip bonding technology for W-band interconnections using alternate lead-free solder bumps

A novel lead-free flip-chip technology for mounting high-speed compound semiconductor ICs, which have a relatively severe limitation regarding high-heat treatment, is presented. Solder bump interconnections of 0.95Sn-0.05Au were successfully fabricated by reflowing multilayer metal film at as low a temperature as 220/spl deg/C. The bumps were designed to have a diameter of 36 /spl mu/m with a gap between the chip and the motherboard of 24 /spl mu/m. The electrical characteristics of flip-chip-mounted coplanar waveguide chips were measured. The deterioration in reflection loss in the flip chip mounting was less than 3 dB for frequencies up to W-band.     

Power complexity of multiplexer-based optoelectronic crossbar switches

The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both unpipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-/spl mu/m CMOS technology is illustrated. The pipelined switch design occupies < 70 mm/sup 2/ of CMOS area, and consumes <80 W of power, which compares favorably to the power required in electrical crossbar switches of equivalent capacity.     

Power minimization in QoS sensitive systems

The majority of modern multimedia and mobile systems have two common denominators: quality-of-service (QoS) requirements, such as latency and synchronization, and strict energy constraints. However, until now no synthesis techniques have been proposed for the design and efficient use of such systems. We have two main objectives: conceptual and synthesis. The conceptual objective is to develop a generic practical technique for the automatic development of online adaptive algorithms from efficient off-line algorithms using statistical techniques. The synthesis objective is to introduce the first design technique for QoS low-power synthesis. We introduce a system of provably-optimal techniques that minimize energy consumption of stream-oriented applications under two main QoS metrics: latency and synchronization. Specifically, we study how multiple voltages can be used to simultaneously satisfy hardware constraints and minimize power consumption while preserving the requested level of QoS. The purpose of the off-line algorithm is threefold. First, it is used as input to statistical software which is used to identify important and relevant parameters of the processes. Second, the algorithm provides buffer occupancy rate indicators. Lastly, it provides a way to combine buffer occupancy and QoS metrics to form a fast and efficient online algorithm. The effectiveness of the algorithms is demonstrated on a number of standard multimedia benchmarks.     

光电振动传感技术新进展

光电振动传感器在振动测量领域占有重要地位,概要叙述了光电振动传感器近年来的最新进展。按测量原理分类介绍了相关技术的发展和取得的成果,并对技术趋势做了总结归纳,指出了一些热点方向。     

Silicon-based optical receivers in BiCMOS technology for advanced optoelectronic integrated circuits

A double photodiode (DPD) and a phototransistor were implemented in an industrial 0.8 μm bipolar complementary metal oxide semiconductor (BiCMOS) n-well process. Both devices are 100% BiCMOS compatible, so that no process modifications were necessary. A −3 dB bandwidth of more than 200 MHz was measured for the DPD. The rise and fall times of the photodiode are less than 1 ns. By an optimized antireflection coating layer for a wavelength of 638 nm a quantum efficiency of η=95%, which corresponds to a responsivity of R=0.49 A/W, is achievable. A phototransistor with a light-sensitive area of 53×53 μm² was developed. Its current amplification of B=300 results in a much larger responsivity compared to the photodiodes. Measurements have shown a −3 dB bandwidth of 7.8 MHz for the phototransistor.     

Monolithic optoelectronic integration: A new component technology for lightwave communications

We discuss recent advances in the field of optoelectronic device integration. Several problems and advantages associated with integration are illustrated by discussing in detail three device types which are currently undergoing intensive investigation: integated laser transmitters, integrated p-i-n photodetector receivers, and arrays of individually addressable detectors and light emitters. Devices fabricated using either GaAS or InP-based material systems with application at wavelength of 0.82-0.87 µm and 1.3-1.55µm, respectively, are considered. It is concluded that the pursuit of optoelectronic integration will lead to an increase in device functionality, an improvement in performance, and a reduction in cost of the integrated device as compared with its hybrid counterpart.     

Monolithic optoelectronic integration: A new component technology for lightwave communications

We discuss recent advances in the field of optoelectronic device integration. Several problems and advantages associated with integration are illustrated by discussing in detail three device types which are currently undergoing intensive investigation: integrated laser transmitters, integrated p-i-n photodetector receivers, and arrays of individually addressable detectors and light emitters. Devices fabricated using either GaAs or InP-based material systems with application at wavelength of0.82-0.87 mum and1.3-1.55 mum, respectively, are considered. It is concluded that the pursuit of optoelectronic integration will lead to an increase in device functionality, an improvement in performance, and a reduction in cost of the integrated device as compared with its hybrid counterpart.     

Power minimization for delivering integrated multimedia servicesover digital subscriber line

We study the problem of designing an efficient resource allocation scheme in the application of providing integrated multimedia services over a digital subscriber line. For a predefined quality of service (QoS) requirement and data throughput, we show that the transmitted power consumption can be reduced by applying the parallel transmission framework previously proposed. Data streams are recognized as a set of layers with different data rate and bit error rate requirements. The characteristics of the telephone channel can be utilized to provide unequal error protection naturally and thus efficiently. Simulation results provide comparison of the proposed parallel transmission framework to the existing schemes designed for general data, and demonstrate significant performance improvement, such as a 0.5-2 dB power gain     

基于光电技术的脉搏测量方法

脉搏测量是指检测脉博的有无,使用的传感器是红外接收二极管和红外发射二极管.信号经过放大后,送入单片机计数测量.为了克服干扰,设计了低通放大器.     

光电信息技术的应用及发展前景分析

光电信息技术被应用在轻武器、医学、生物医药、深海探测等领域中,给各个领域都带来了前所未有的发展,光学信息技术的应用情况已成为衡量一个国家综合实力的标志。文章就光电信息技术的发展现状进行分析,研究其应用状况和发展前景。     

Optical interconnections for VLSI systems

The combination of decreasing feature sizes and increasing chip sizes is leading to a communication crisis in the area of VLSI circuits and systems. It is anticipated that the speeds of MOS circuits will soon be limited by interconnection delays, rather than gate delays. This paper investigates the possibility of applying optical and electrooptical technologies to such interconnection problems. The origins of the communication crisis are discussed. Those aspects of electrooptic technology that are applicable to the generation, routing, and detection of light at the level of chips and boards are reviewed. Algorithmic implications of interconnections are discussed, with emphasis on the definition of a hierarchy of interconnection problems from the signal-processing area having an increasing level of complexity. One potential application of optical interconnections is to the problem of clock distribution, for which a single signal must be routed to many parts of a chip or board. More complex is the problem of supplying data interconnections via optical technology. Areas in need of future research are identified.     

Optical interconnections for parallel and distributed computing

This paper reports the application of optical interconnections to a parallel an distributed computing system in the form of a calibration-free 64-Gbps/board parallel optical interconnection sub-system mounted directly on the four-CPU processor board of a newly developed parallel-processing machine, “RWC-1”. The sub-system is composed of eight parallel optical module/single-chip link large-scale integrated circuit pairs. The subsystem successfully transmitted parallel data for a variety of link lengths (between 1 m and 1 km), and with deskewing and synchronizing functions, phase-matching calibration for link lengths is automatic. Further, a method is described for the simplified merging of optical interconnections into electronic systems     

光电探测技术在火控系统中的应用及发展

针对新型光电火控系统的应用和发展,结合光电探测技术在火控系统中的具体应用,对配备了光电传感器(激光测距、电视跟踪、红外跟踪)的新型光电火控系统的特点进行了分析。并以洛克希德.马丁公司为美国海军陆战队的AH-1Z"眼镜蛇"直升机研制的光电火控目标瞄准系统(TSS)为例,对目前世界上先进的多传感器火控系统的主要性能参数和功能特性进行了分析,并初步探讨了新型光电火控系统的发展趋势,即光电火控系统正朝着各光电系统光轴合一、功能多样化、多目标跟踪的方向发展。新型光电火控系统将进一步提高目标识别、定位距离和装备平台的存活能力。     

Regenerative feedback repeaters for programmable interconnections

The use of regenerative feedback repeaters to reduce the delay in programmable interconnections is described. A static, complementary regenerative feedback (CRF) repeater is proposed. This CRF repeater locally regenerates the new level for a fixed time after a transition has been detected. Design issues and limitations are discussed. It is shown that rising transitions can propagate faster than falling transitions through a chain of overdriven nMOS switches with CRF repeaters. Experimental results from a 1.2 μm CMOS implementation show that the loaded delay through 64 switches for static and dynamic repeaters can be reduced by a factor 1.4-2 over conventional repeaters     

Reconfigurable optical interconnections for parallel computing

We describe our research on optically interconnected optoelectronic parallel computing systems. Our architecture is based on a multilayer pipeline of two-dimensional optoelectronic device arrays in which each pixel is composed of an optical input channel, a general-purpose programmable processor, local memory, and a surface-emitting laser diode as an optical output channel. Free-space optics provides parallel, global communication between layers in the pipeline via optical paths that are dynamically reconfigurable. Design and initial realization of a system are described