新型D/A变换器AD9755及其应用

AD9755是Analog Device公司生产的一种14位高速数模转换芯片,其特有的双端数据复用结构,使之获得了优越的DAC性能.在介绍了AD9755的工作原理基础上,阐述了其在任意波形产生器中的设计应用.     

基于DDS的模拟调制系统设计

随着FPGA在速度和资源方面的快速发展,各种复杂的模拟调制信号也可以用数字化的形式实现。这与传统的模拟方法实现相比,各种调制信号数字化实现具有更多的灵活性、精确性、可控性,使其得到更广泛的应用。这里基于全数字化频率合成器（DDS）技术,用现场可编程门阵列（FPGA）、AD9755数字化实现调幅（AM）、线性调频（FM）、非线性FM调制。     

革新技术的强势组合——ONKYO(安桥)A-9755放大器与DX-7555 CD播放机组合

A-9755立体声放大器与DX-7555 CD播放机其实也算不上新产品,在2005年广州音响唱片展上也曾亮过相,但是到2006年底才正式登陆国内。当然,就ONKYO的纯Hi-Fi产品而言,这确实又是最新的型号。A-9755最大的亮点就是采用了数字放大技术,对于ONKYO来说,数字放大技术也并非首次采用。这是其开发的最新VL Digital技术,在经过前几代的摸索之后,在A-9755身上运用得更自如、技术更成熟。DX-7555最吸引眼球的地方是采用了高精度的时钟电路,精确度达到只有±1．5 ppm的误差。以下就逐一分析一下A-9755放大器与DX-7555 CD播放器所使用的焦点技术。     

VGA芯片AD600及其在有效值（dB）线性测量电路中的应用

本文在介绍AD600芯片的特点和原理的基础上，阐述了在不同要求下AD600的应用，给出由AD600和AD636构成的80dB动态范围有效值（dB）线性测量电路，并对其宗标方法作了简要说明。     

功率检测器AD8318的特点及应用

介绍了AD8318的性能特点，引脚功能，分析了AD8318内部结构和功能实现，并给出了其在射频信号转换中典型应用电路。     

并行D/A转换器件AD7547及其接口设计

AD7547是AD公司制造的一种双路12位数模转换器件，本文简要介绍了其基本结构和引脚功能，并结合实际阐述了其在计算机扩展板卡中的应用设计。     

并行D/A转换器AD7846及其接口设计

AD7846是AD公司制造的一种16位数模转换器件，本文简要介绍了其基本结构和引脚功能，并结合实际阐述了其在大幅面激光标刻控制卡中的应用设计，总结了高精度D／A转换电路设计中抗干扰的一些基本方法。     

ADI公司连续推出其16bit和18bit PuISAR ADC

ADI公司通过提供不仅超快速而且超高精度的16bit和18bit ADC，不断地建立业界标准。我们为16bit的AD7621建立了3MSPS转换速率条件下的速度和性能标准，并且为18bit的AD7641建立了2MSPS转换速率条件下的速度和性能标准。对于需要以至高精度转换快速变化信号的设计工程师来说，AD7621和AD7641是理想的选择。许多应用都可以利用AD7621和AD7641在精度和速度方面绝妙的结合，其中医学图像处理、高速数据采集和自动测试设备只是几个应用实例。AD7621和AD7641在单片ADC中提供了完整的模拟功能，从而能够简化设计过程并且大幅度降低成本。这两种器件具有的经过验证的高精度允许只用最少的模拟前端和滤波器校准就能完成低电平信号的转换，从而减少了设计工作量、成本，并且显著加快产品面世时间。     

AD515A在电压测量电路中的应用

介绍了静电计专用集成运放AD515A的结构特点，提出了一种基于AD515A的高精度实时测量累计电压的方法。该方法采用AD515A和一个积分电容构成基本测量电路，不仅捉高了测量的稳定性，而且可使其校准和调整更加方便。     

芯片AD9854在跳频通信系统中的应用

介绍了AD公司新推出的AD9854芯片的主要特性，讨论了将其应用于跳频通信系统中的优势。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.