共查询到19条相似文献,搜索用时 160 毫秒
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为解决纳米CMOS工艺下单粒子多节点翻转的问题,提出了一种加固存储单元(RH-12T)。在Quatro-10T存储单元基础上对电路结构进行改进,使存“0”节点不受高能粒子入射的影响,敏感节点对的数目是晶体管双立互锁(DICE)存储单元的一半。基于敏感节点对分离和SET缩减原理,进行了加固存储单元版图设计。在相同设计方法下,该存储单元的敏感节点间距是DICE存储单元的3倍。抗SEU仿真结果表明,该存储单元具备单节点翻转全加固能力。全物理模型单粒子瞬态仿真结果表明,该存储单元的线性能量转移 (LET)翻转阈值为DICE存储单元的2.8倍,能有效缓解单粒子多节点翻转的问题。 相似文献
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空间环境中存在大量的高能带电粒子,空天导弹自身的电子器件将会受到高能粒子的冲击影响,从而产生单粒子效应。研究分析了静态储存器在空间环境中最常发生的单粒子效应-单粒子翻转,采用修正海明码实现一个检错纠错模块,该模块可以检测数据存储单元的两位错误,检测定位并纠正数据存储单元的一位错误。通过仿真分析及计算,该方案可以很大程度上降低单粒子翻转效应对静态存储器的影响,具有很强的实用意义。 相似文献
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在空间辐射环境下,存储单元对单粒子翻转的敏感性日益增强。通过比较SRAM的单粒子翻转效应相关加固技术,在传统EDAC技术的基础上,增加少量硬件模块,有效利用双端口SRAM的端口资源,提出了一种新的周期可控定时刷新机制,实现了对存储单元数据的周期性纠错检错。对加固SRAM单元进行分析和仿真,结果表明,在保证存储单元数据被正常存取的前提下,定时刷新机制的引入很大程度地降低了单粒子翻转引起的错误累积效应,有效降低了SRAM出现软错误的概率。 相似文献
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分析了三模冗余(TMR)型D触发器和双互锁存储单元(DICE)型D触发器各自的优点和缺点,基于三模冗余和双互锁存储单元技术的(TMRDICE)相融合方法,设计实现了基于双互锁存储单元技术的三模冗余D触发器。从电路级研究了TMRDICE型D触发器抗单粒子翻转的性能,与其他传统类型电路结构的D触发器进行了抗单粒子翻转性能比较,并通过电路仿真和辐照实验进行了验证。仿真结果表明,TMRDICE型D触发器的抗单粒子翻转性能明显优于传统的普通D触发器、TMR型D触发器和DICE型D触发器。辐照实验结果表明,TMRDICE型D触发器具有最小的翻转截面。 相似文献
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Egas Henes Neto Gilson Wirth Fernanda Lima Kastensmidt 《Journal of Electronic Testing》2008,24(5):425-437
In this paper, we propose a diagnose strategy based on built-in current sensors able to detect the effects of single event
transients (SETs) in SRAM memory decoders. By analyzing the effects, it is possible to mitigate the error by warning the system
about the erroneous write and read operation or by circuit error correction avoiding catastrophic multiple bit upset errors.
While EDAC can only protect faults in the memory cell array, the proposed method can cope with faults in the combinational
memory circuitry. This BICS-based technique can be used in combination with EDAC to achieve high reliability in memories fabricated
in nanometer technologies. Our methodology has been validated by Spice simulation and results show that our approach presents
a low area, performance and power dissipation penalty. 相似文献
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We demonstrate a voltage-readable nonvolatile memory cell with programmable ferroelectric multistates in an organic inverter configuration. The intermediate memory states of a ferroelectric gate insulator, varying with the magnitude of the programming voltage, allow the multilevels of the drain current at zero gate-source voltage in a ferroelectric organic field-effect transistor (OFET). The current output from the ferroelectric memory is directly converted into the voltage-readable output in a zero-gate load inverter configuration where both a driving paraelectric OFET having a paraelectric buffer layer and a load ferroelectric OFET are monolithically integrated in a single substrate. The multilevel voltage-readable output characteristics are obtained from the ferroelectric multistates as a function of the programming voltage. 相似文献
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In principle, a memory field-effect transistor (FET) based on the metal-ferroelectric-semiconductor gate stack could be the building block of an ideal memory technology that offers random access, high speed, low power, high density and nonvolatility. In practice, however, so far none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days, a far cry from the ten-year retention requirement for a nonvolatile memory device. This work will examine two major causes of the short retention (assuming no significant mobile ionic charge motion in the ferroelectric film): 1) depolarization field and 2) finite gate leakage current. A possible solution to the memory retention problem will be suggested, which involves the growth of single-crystal, single domain ferroelectric on Si. The use of the ferroelectric memory transistor as a capacitor-less DRAM cell will also be proposed 相似文献
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Verification was sought for the memory operation of a single transistor type ferroelectric random access memory (1T type FeRAM) with a circuit model for a memory cell transistor combined with a precharged capacitive decoupling sensing scheme. The wiring scheme of the 1T type FeRAM array was also proposed based on the operation of the fabricated memory cell transistor. As a result, the memory operation of 1T type FeRAM was confirmed at a low current level with high sensing speed and no reference cell, and the design and verification of the full chip were achieved. 相似文献
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This paper describes an experimental static memory cell in GaAs MESFET technology. The memory cell has been implemented using a mix of several techniques already published in order to overcome some of their principal drawbacks related to ground shifting, destructive readout, and leakage current effects. The cell size is 36×37 μm2 using a 0.6-μm technology. An experimental 32 word × 32 bit array has been designed. From simulation results, an address access time of 1 ns has been obtained. A small 8 word×4 bit protoype was fabricated. The cell can be operated at the single supply voltage from 1 up to 2 V. The evaluation is provided according to the functionality and power dissipation. Measured results show a total current consumption of 14 μA/cell when operated at 1 V 相似文献
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《Electron Device Letters, IEEE》1985,6(8):422-424
An advance in the simulation of a single event upset (SEU) of a static memory is achieved by combining transport and circuit effects in a single calculation. The program SIFCOD [4] is applied to the four transistors of a CMOS SRAM cell to determine its transient circuit response following a very high energy ion hit. Results unique to this type of calculation include determination of relative upset sensitivites and different upset mechanisms for specific area hits, i.e., the OFF p-channel drain, the OFF or ON n-channel drain, etc. The calculation determines the transport variables as a function of time in two-space dimensions for each of the four transistors and provides the nodal voltage and current responses for assessing memory upset conditions. 相似文献
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Kobayashi D. Shibata T. Fujimori Y. Nakamura T. Takasu H. 《Electron Devices, IEEE Transactions on》2005,52(10):2188-2197
A ferroelectric associative memory technology has been developed using ferroelectric materials as a means of storing template vector information. In order to accommodate the ferroelectric memory cell to associative processing circuits, a heterogate floating-gate MOS structure has been developed. As a result, nondestructive reading of analog data written in the ferroelectric film has been made possible, allowing a wide voltage range of input signals to associative processing circuits. The concept has been experimentally verified using fabricated test devices and circuits. 相似文献
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针对应变Si NMOS器件总剂量辐射对单粒子效应的影响机制,采用计算机TCAD仿真进行研究。通过对比实验结果,构建50 nm应变Si NMOS器件的TCAD仿真模型,并使用该模型研究处于截至态(Vds=1 V)的NMOS器件在总剂量条件下的单粒子效应。实验结果表明,总剂量辐照引入的氧化层陷阱正电荷使得体区电势升高,加剧了NMOS器件的单粒子效应。在2 kGy总剂量辐照下,漏极瞬态电流增加4.88%,而漏极收集电荷增量高达29.15%,表明总剂量辐射对单粒子效应的影响主要体现在漏极收集电荷的大幅增加方面。 相似文献
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Yeonbae Chung Byung-Gil Jeon Kang-Deog Suh 《Solid-State Circuits, IEEE Journal of》2000,35(5):697-704
This paper presents, for the first time, a 4-Mb ferroelectric random access memory, which has been designed and fabricated with 0.6-μm ferroelectric storage cell integrated CMOS technology. In order to achieve a stable cell operation, novel design techniques robust to unstable cell capacitors are proposed: (1) double-pulsed plate read/write-back scheme; (2) complementary data preset reference circuitry; (3) relaxation/fatigue/imprint-free reference voltage generator; (4) open bitline cell array; (5) unintentional power-off data protection scheme. Additionally, to improve cell array layout efficiency a selectively driven cell plate scheme has been devised. The prototype chip incorporating these circuit schemes shows 75 ns access time and 21-mA active current at 3.3 V, 25°C, 110-ns minimum cycle. The die size is 116 mm2 using 9 μm2, one-transistor/one-capacitor-based memory cell, twin-well, single-poly, single-tungsten, and double-Al process technology 相似文献