ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance–flexibility figures in the respective algorithmic class.

KAIST image computing system (KICS): A parallel architecture for real-time multimedia data processing

An efficient parallel architecture is proposed for high-performance multimedia data processing using multiple multimedia video processors (MVP; TMS320C80), which are fully programmable general digital signal processors (DSP). This paper describes several requirements for a multimedia data processing system and the system architecture of an image computing system called the KAIST Image Computing System (KICS). The performance of the KICS is evaluated in terms of its I/O bandwidth and the execution time for some image processing functions. An application of the KICS to the real-time Moving Picture Expert Group 2 (MPEG-2) encoder is introduced. The programmability and the high-speed data-access capability of the KICS are its most important features as a high-performance system for real-time multimedia data processing.     

A real-time image processor with combining dynamic contrast ratio enhancement and inverse gamma correction for PDP

Inverse gamma correction must be performed before displaying the received video signal because alternating current plasma display panel (AC PDP) has a linear output luminance response to a digital-valued input. At the same time contrast ratio enhancement is necessary for improving the image quality of display devices. The histogram equalization (HE) is an important contrast ratio enhancement method. But sometimes HE can produce unrealistic effects in images. In this paper, a new method of combining dynamic contrast ratio enhancement and inverse gamma correction for AC PDP is proposed. The dynamic contrast ratio enhancement and the inverse gamma correction are realized simultaneously in the proposed method. Furthermore the over-enhancement caused by the traditional HE can be avoided. A real-time image processor with the proposed method was designed and implemented. Simulations and experimental results on a 50-in. AC PDP show that the image quality of AC PDP can be improved obviously.     

基于DSP的沥青路面裂缝图像处理系统研究

裂缝的检测是公路养护的重要工作之一,在分析沥青路面图像特点的基础上,研究设计了基于DSP的沥青路面裂缝图像处理系统,结合DSP技术给出了解决沥青路面裂缝图像处理系统中DSP图像采集部分问题的方法,完成了对裂缝的面积、周长、类型、长度、平均宽度,裂缝的百分比等主要参数的提取.通过采用该图像采集系统进行的大量野外实验,对在车辆高速行驶状态下采集到的连续图像的效果进行比较分析以及处理,最后结果表明了该图像采集与处理系统设计的可行性和实用性.     

Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing

Technology evolution makes possible the integration of heterogeneous components as programmable elements (processors), hardware dedicated blocks, hierarchical memories and buses. Furthermore, an optimized reconfigurable logic core embedded within a System-on-Chip will associate the performances of dedicated architecture and the flexibility of programmable ones. In order to increase performances, some of the applications are carried out in hardware, using dynamically reconfigurable logic, rather than software, using programmable elements. This approach offers a suitable hardware support to design malleable systems able to adapt themselves to a specific application. This article makes a synthesis of the Ardoise project. The first objective of Ardoise project was to design and to produce a dynamically reconfigurable platform based on commercial FPGAs. The concept of dynamically reconfigurable architecture depends partially on new design methodologies elaboration as well as on the programming environment. The platform architecture was designed to be suitable for real-time image processing. The article outlines mainly the Ardoise tools aspect: development environment and real-time management of the hardware tasks. The proposed methodology is based on a dynamic management of tasks according to an application scenario written using C++ language.

基于DSP和FPGA的被动声探测实时采集系统设计

为了给被动声探测技术研究提供实验验证平台,设计了一种可以进行实时数据采集和处理的系统方案.整个系统以数字信号处理器(DSP)和现场可编程门阵列(FPGA)为基本架构,由FPGA控制模数转换器(ADC)采集数据,通过USB 2.0电路将数据传送给个人计算机(PC),用于初期的离线验证;FPGA将采集到的数据通过外部存储器接口(EMIF)传递给DSP,用于实时处理.实验证明:系统实现了被动声探测中的实时数据采集、离线数据存储.数据采集与数据处理分别由不同处理器执行,提高了系统的响应速度与处理性能,能够满足探测系统的实时性要求.     

红外小目标检测跟踪系统设计

从图像处理方法的角度对红外图像中小目标的检测、跟踪进行了研究,给出了系统总体设计框图,整个检测算法的前端图像滤波预处理采用FPGA实现,识别跟踪采用DSP实现。详细介绍了系统各功能模块的设计方法。实验表明该系统实现了小目标检测跟踪的功能,工作稳定可靠。     

FDI based on an adaptive observer for current and speed sensors of PMSM drives

This paper deals with a new method of current and speed sensors faults detection isolation (FDI) and identification for a permanent magnet synchronous motor (PMSM) drives. A new state variable is introduced so that an augmented system can be constructed to treat PMSM sensor faults as actuator faults. This method uses the PMSM model and a bank of adaptive observers to generate residuals. The residuals results are used for sensor fault detection. A logic algorithm is built in such a way to isolate and identify the faulty sensor for a stator phase current fault after detecting the fault occurrence. Simulation results are presented to illustrate the functionality of theoretical developments. Experimental results with 1.1-kW PMSM have validated the effectiveness of the proposed FDI method. The experimental implementation is carried out on powerful dSpace DS1103 controller board based on the DSP TMS320F240.     

基于加速度信号的过山车监测预警系统设计

鉴于国家对特种设备安全的要求和大型游乐设施测试系统的现状,设计了一种过山车监测预警系统。系统的信号采集装置安装在过山车上,采用数字信号处理器(DSP)作为主控芯片,运算速度快,可实现数据的实时采集,硬件电路多采用3.3V的低功耗芯片,节能环保。系统采集高频振动加速度和低频运动加速度信号,通过WiFi将数据传输给上位机,上位机软件使用LabVIEW开发,运用小波分析处理数据,并采用BP神经网络算法诊断故障,同时,对采集的信号和标准信号进行快速傅立叶变换(FFT)分析并作频谱图,可直观的检验诊断结果。如果诊断出故障,系统可发出警报并通过通用分组无线业务(GPRS)通知相关工作人员。实验结果表明:系统的运算速度快,诊断结果可靠。     

基于DSP的无人机遥感影像SIFT算法设计与实现

为了满足尺度不变特征变换（SIFT）算法临场处理大尺寸无人机（UAV）组网遥感观测影像的实时快速需求,提出一种基于数字信号处理器（DSP）内核的硬件乘法器来处理单精度浮点型像素数据乘法的算法实现方案。首先,根据DSP内核的硬件乘法器的数据输入、输出特性,重构SIFT算法的图像数据结构和图像函数,以实现硬件乘法器对SIFT算法单精度浮点型像素数据的乘法计算;其次,采用软件流水技术重新编排迭代计算,以增强算法的并行计算能力;最后,将在算法计算过程中产生的动态数据迁移至第三代双倍速率同步动态随机存储器（DDR3）中,以提升算法数据的存储空间。实验结果表明,DSP平台的SIFT算法可以实现对1 000×750的UAV遥感影像的高精度快速处理,所提方案满足无人机组网遥感影像临场处理对SIFT算法的实时快速要求。     

基于DSP的静电悬浮转子微陀螺测控系统

开发了一种基于数字信号处理器(DSP)的静电悬浮转子微陀螺的可视化闭环测控系统.该系统是在VC33DSP平台下,采用增量式PID算法控制器,对VC33DSP开发系统的外设A/D、D/A和PCI芯片进行编程应用.具体为使用VC++编写可视化界面,对PCI芯片编程实现DSP与PC之间通信,使用VC33DSP汇编语言编程实现数据的输入输出.经编程测试,增量式汇编函数能够有效运行,为静电悬浮转子微陀螺的悬浮、旋转等检测控制实现奠定了一定的基础.