Computing the Average Symbol Error Probability of the MPSK System Having Quadrature Error

When quadrature error exists, the shape of the M‐ary phase shift keying (MPSK) signal constellation becomes skewed‐elliptic. Each MPSK symbol takes on a different symbol error probability (SEP) value. The analytical results presented thus far have been derived from studies which examined the SEP problem assuming that the SEP of each MPSK symbol is equally likely; therefore, those results should not be treated as offering a complete solution. In this letter, we present a new and more complete solution to the SEP problem of MPSK by relaxing the above assumption and finding the expressions for the average as well as individual SEP in the presence of quadrature error.     

Baseband Digital Predistorter with Quadrature Error Correction

In this article simulation and measurement results of a FPGA implementation of a baseband digital complex gain predistorter with a quadrature modulator and demodulation error correction circuits are presented. Four different methods for finding the quadrature error correction values are compared and the effect of quadrature errors to predistortion is discussed. A 50 dB three stage power amplifier chain with an analog quadrature modulator and demodulator was used in the measurements as the device to be predistorted. The signal used in the measurements and simulations was a 30 dBm 18 kHz 16-QAM signal at 400 MHz carrier frequency. In the measurements 15 dB reduction in 3rd order nonlinearity was achieved. The usage of quadrature error correction reduced the adjacent channel power by 9 dB. Ilari Teikari was born in Tampere, Finland, in 1978. He received the M.Sc. (tech.) degree from Helsinki University of Technology (HUT), Helsinki, Finland, in 2002. He is currently working toward D.Sc. (tech) degree in the electronic circuit design laboratory, HUT. His current research intrests are in the area of power amplifier linearization methods and digital circuit design. Jouko Vankka was born in Helsinki, Finland, in 1965. He received the M.S. and Ph.D. degrees in electrical engineering from Helsinki University of Technology (HUT) in 1991 and 2000, respectively. Since 1995, he has been with the Electronic Circuit Design Laboratory, HUT. His research interests include VLSI architectures and mixed-signal integrated circuits for communication applications. Kari A. I. Halonen was born in Helsinki, Finland, on May 23, 1958. He received the M.Sc. degree in electrical engineering from Helsinki University of Technology, Finland, in 1982, and the Ph.D. degree in electrical engineering from the Katholieke Universiteit Leuven, in Heverlee, Belgium, in 1987. From 1982 to 1984 he was employed as assistant at Helsinki University of Technology and as research assistant at the Technical Research Center of Finland. From 1984 to 1987 he was a research assistant at the E.S.A.T. Laboratory of the Katholieke Universiteit Leuven, enjoying also a temporary grant of the Academy of Finland. Since 1988 he has been with the Electronic Circuit Design Laboratory, Helsinki University of Technology, as senior assistant (1988–1990), and the director of the Integrated Circuit Design Unit of the Microelectronics Center (1990–1993). He was on leave of absence the academic year 1992–1993, acting as R&D manager in Fincitec Inc., Finland. From 1993 to 1996 he has been an associate professor, and since 1997 a full professor at the Faculty of Electrical Engineering and Telecommunications, Helsinki University of Technology. He became the Head of Electronic Circuit Design Laboratory year 1998. From 1997 to 1999 he was an associate editor of IEEE Transactions on Circuits and Systems I. He has been a guest editor for IEEE Journal of Solid-State Circuits and the Technical Program Committee Chairman for European Solid-State Circuits Conference year 2000. He has been awarded the Beatrice Winner Award in ISSCC'02 Conference year 2002. He specializes in CMOS and BiCMOS analog integrated circuits, particularly for telecommunication applications. He is author or co-author over a hundred and fifty international and national conference and journal publications on analog integrated circuits. He has several patents on analog integrated circuits.     

超宽带冲击脉冲正交解调接收机幅相误差分析与校正算法

对脉冲体制的超宽带正交解调接收机幅相误差模型进行了深入分析。并基于冲击脉冲信号形式,提出新的正交解调接收机幅相误差分析与校正算法。弥补了现有的基于线性调频信号形式而提出的超宽带正交解调误差校正算法的不足,其更普适于各种超宽带信号形式。在实际系统中获得了理想的效果。     

一种用于蓝牙系统的延迟锁相正交信号发生器

提出了一种延迟锁相结构的正交信号发生器 ,用于蓝牙的射频信号收发电路。介绍的延迟锁相环路结构使电路性能具有良好的工艺变化不相关性 ,在很宽的频带范围内均可获得高性能的正交信号。电路采用单层多晶硅、四层金属、0 .3 5 μm CMOS数字工艺实现 ,仿真结果表明 :电路稳定工作在 2 .45 GHz频率下 ,在 1 40 MHz的输入信号频率变化范围内 ,输出的正交信号相位偏差低于 1°,幅度偏差小于 5 %。电路主要由有源器件构成 ,面积小     

正交调制过程的误差分析

在正交调制的实现过程中有四路输入信号，每路输入信号都不可避免的引入误差。本文主要讨论引入的线性误差对已调信号的影响，并提出了改善方法。     

脉间变频测量雷达正交误差的实时修正方法

针对脉间变频RCS测量雷达采用模拟正交解调方法获得同相分量和正交分量所引入的解调误差,提出了一种实时校准方法。该方法通过引入校准支路,将从测试信号耦合出的校准信号经固定延时和衰减后与回波信号在同一个脉冲周期内依先后顺序采集,由于校准支路信号只与系统内部状态有关而与测试目标和场地无关且间隔很短,可使用校准支路所得到的误差校准测试通道的信号。通过校准支路的应用可在系统整个工作时间内随时对解调误差进行修正。给出了校准支路的分析及设计,对使用模拟器测试的结果讨论了修正算法。     

模拟正交调制误差数字校正方法

模拟正交调制可有效降低对FPGA等数字器件的工作频率要求,特别适合于高等级大规模高速FPGA器件受到限制的星载设备及军用设备研制场合。但由于器件指标限制及电路的不一致性,模拟正交调制存在较大的电路误差,而通过电路设计和调试将误差减小的工程实现难度较大。提出一种数字校正方法,通过在基带信号引入2个校正因子,可有效校正模拟正交调制的电路误差,完全满足正交不平衡度小于1°、幅度不平衡度小于0.2dB的指标需求。     

正交检波器通道间平衡性能测试的线性回归方法

提出了一种测量正交检波器通道间幅度不平衡性和相位不平衡性的新方法——线性回归方法，并用计算机进行了数值模拟。模拟结果表明，该方法的计算精度很高。     

误差通道建模误差对多误差LMS算法性能的影响

本文证明了，在多通道自适应宽带有源噪声控制中，由于误差通道建模误差的存在，多误差LMS算法是条件收敛的，并推导了保证算法收敛的条件，还证明了，算法收敛后，得到自适应滤波器权值一般只是理论上最优值的有偏估计，计算机仿真结果验证了所得结论．     

调制误差对相关损失的影响分析

相关损失作为反映导航信号质量的重要指标之一,与接收机跟踪误差、解调门限以及捕获能力相关联。选取信号生成过程中调制误差作为误差源,在考虑两路信号调制的情况下,导出了全匹配接收和单路接收处理时相关损失解析表达式。分析了幅度不平衡度和相位正交误差对相关损失的影响以及全匹配接收和单路接收时相关损失的差异。结果可以为信号生成过程中的误差评估和预算以及导航信号质量评估提供参考,同时分析结果仍然适用于其他采用直接扩频通信的系统。     

基于正交上变频器的宽带DDS设计

数字直接频率合成器（DDS）广泛应用于雷达、对抗、通信等领域。利用2个DDS产生频率一致、相位正交的基带I、Q信号,通过正交上变频器,获得2倍于单个DDS带宽的宽带DDS,该方法有效提高了DDS的信号带宽。     

乘积型相位鉴频器的深入分析

详细分析了乘积型相位鉴频器，推导了鉴频特性的解析公式，分析了近似公式的误差及应用范围，讨论了鉴频灵敏度与电路参数的关系。     

一种用于信号分析的数字正交解调电路设计

阐述了数字正交解调的原理以及与传统模拟正交解调相比所体现出的优越性。详细介绍了一种用于信号分析的数字正交解调电路设计方案和工作原理,并结合信号分析类仪器的特点和要求说明电路的硬件和软件设计方法。通过对数字滤波环节的仿真和在具体应用中所得到的实验结果说明设计电路的优越性。     

DBF系统的数字正交相干检波设计

结合某具体工程实例讨论了带通信号采样定理,在此基础上研究了数字正交相干检波技术的优化设计.计算机仿真和性能分析表明,该设计对其他工程具有一定的参考价值.     

一种无人机载合成孔径雷达宽带波形产生及正交接收的实验研究

对无人机载合成孔径雷达的宽带波形产生及正交接收进行了分析、研究,给出了基于数字直读和模拟正交解调的实验结果,该技术已应用于某超宽带VHF/UHF合成孔径雷达中,取得了较好的效果。     

一种基于正交调制技术的宽带频率源设计

针对传统DDS内插PLL频率合成方法的某些不足,提出了一种新的基于正交调制技术的频率合成方法,该方法容易实现频率源的宽带小步进输出,且电路形式简单。最后给出了一个该方法的应用实例设计,为宽带小步进频率源的设计提供了较好的思路。     

数字正交FM解调方案门限效应的研究

介绍了FM解调方案的门限效应。针对传统调频解调方案中的解调门限值高以及降低解调门限的方案难以实现的不足,在研究传统模拟调频解调方案的基础上,分析了数字FM解调方案的门限性能。理论推导证明,数字正交FM解调方案的门限效应低于模拟解调方案。因此,可以采用数字正交解调方案降低其解调门限,而不需采用较难设计和控制的反馈系统,这极大地降低了调频系统实现的复杂度。最后计算机仿真的结果显示,该方案比传统模拟解调方案门限约低2dB。     

正交解调误差对宽带波束形成的影响

 宽带相控阵雷达中解调误差的存在会对自适应宽带波束形成造成影响.论文以宽带信号和正交解调误差模型为基础,求解了时域和频域宽带波束形成中自相关矩阵的表达式.通过对自相关矩阵的分析论文指出,误差会引起干扰自由度增加、波束形成性能下降.在宽带波束形成中需要更多的空间自由度.     

正交插值与脉冲压缩的最佳滤波器设计

提出了以吞吐率最大为准则利用频域分段算法进行FIR滤波的方法.推导了雷达信号处理中正交插值和脉冲压缩处理的频域算法,针对长信号序列的频域滤波处理,研究了分段滤波方法,得出了最佳分段长度.并将正交插值和脉冲压缩处理在频域合并起来,进一步降低了运算量.     

模拟面目标中频正交幅度调制系统

介绍了为某产品研制的模拟面目标中频正交幅度调制系统，其输出的调制信号频率为120MHz，1dB带宽较宽，合成输出脉冲宽度为9．145μs，杂波电平为-33dBm。可模拟的面目标最小高度为15m。