展讯通信：高清AVS／MPEG-2系统级解码核芯片SV6111

展讯通信公司将于CCBN 2008推出高清AVS／MPEG-2系统级解码核芯片SV6111。 该芯片是一款先进的基于AVS标准和MPEG-2标准的机顶盒系统级解码芯片,主要应用于网络电视、有线数字电视、卫星数字电视和地面传输数字电视等多媒体领域。它支持AVS标准和MPEG-2标准的高清（HD）和标清（SD）的视频解码,同时支持多种流行的音频标准（如MPEG-1 Layer Ⅰ＆Ⅱ＆Ⅲ,AC3,AVS等）的音频解码。     

音频工作站MPEG-Ⅰ Layer-Ⅱ码流快速解码混音

为了能实时完成数字音频工作站中多路MPEG-Ⅰ Layer-Ⅱ音频压缩码流的快速解码混音,在分析MPEG-Ⅰ解码器中的多相滤波器组这个核心算法的基础上,提出了多路MPEG-Ⅰ Layer-Ⅱ码流的快速解码混音算法.此算法在进行混音计算时,只需做一次在解码中较为费时的子带综合滤波计算,大大提高了多路混音的速度.实验表明,用该算法进行8路MPEG-Ⅰ Layer-Ⅱ解码混音时,在PI-Ⅱ 600MHz的PC机达到了0.25倍实时的解码速度,完全满足了专业数字音频工作站的要求.     

HDTV SoC平台中的MPEG-2变长码解码芯片设计

提出了一种适用于高清晰度数字电视片上系统的MPEG-2变长码解码结构,采用MIPS 4KcTM嵌入式CPU,在AM-BA总线的基础上设计了系统总线和系统的工作流程.根据MPEG-2视频码流的层次特点,模块间采用数据驱动结构,使用两级桶形移位寄存器实现并行解码结构,可缩短关键路径并简化控制逻辑.用硬件描述语言进行描述并通过逻辑功能仿真,用0.18μm CMOS工艺综合了变长码解码的RTL代码,时钟频率达到150 MHz,并在XC6000型FPGA上通过验证.     

AMBA 2.0总线IP核的设计与实现

文章采用Top—Down的方法设计了AMBA2．0总线IP核，它包括AHB和APB两个子IP核。所有AMBA结构模块均实现了RTL级建模，对其中较复杂的仲裁器和AHB／APB桥模块给出了详细的描述。该IP完成了FPGA的验证，最高频率为53．6MHz。在ASIC0．18μm标准单元库下对该IP进行综合与优化，最高频率可以达到150MHz。     

一种高速HUFFMAN解码电路

研究了HUFFMAN解码器在集成电路上的实现问题，以MPEG-2AAC(先进音频编码)HUFFMA为研究对象．在研究解码码表的特点以及简化解码算法的基础上设计出高速HUFFMAN解码电路。此解码电路已经在ALTERA的FPGA上通过测试。系统能稳定运行在100MHz，输出数据平均达到约1．0Gbits／sec的带宽。     

MPEG-2音频解码算法优化

以PC机为硬件平台对MPEG-2的音频解码算法进行优化，实现MPEG-2全软件的系统、视频、音频3个部分实时解码。在IDCT和IMDCT中应用了新的快速算法；结合PC机本身的特点及解码过程中有大量的乘加运算采用SIMD(single—instruction multiple—data)来对程序优化，并在实际运算中也对数据结构进行了优化。通过以上的优化使MPEG-2层Ⅱ解码的运算量减少了40％以上，在奔腾3／450计算机上只占用不到5％的系统资源。这些优化算法已经应用于奔腾3／800为硬件平台的MPEG-2实时解码器中。     

新型编码格式在IP流播出系统的应用

介绍了解包和解码两种模式,并探讨了视频MPEG-2、H.264/AVC、H.265/HEVC和音频MPEG-1 Layer2、AC3编码方式在IP流播出系统中的应用。     

基于NiosⅡ的音频播放器设计与驱动开发

采用TOP—DOWN设计方法,在DE2开发平台上完成音频播放器设计。设计主要包括NiosⅡ软核处理器、音频控制器、I^2C控制器和IDE接口等IP核构成的NiosⅡ系统．在此基础上完成μClinux操作系统移植以及完成基于HAL层的音频驱动器的驱动程序开发,最后用C语言在NiosⅡ系统上编写应用程序进行测试。该实现方法即是下一代消费类电子发展的趋势,也是集成电路发展的一个趋势。     

基于SoC平台的H.264/MPEG-4 AVC解码器设计

提出了一种基于SoC平台的H.264/MPEG-4 AVC解码器设计方案,该方案基于Gaisler Research开发的LEON3 RISC核,采用双总线的流水线结构,具有很高的性价比,通过在Modelsim 6.0下的仿真结果表明,硬件解码部分在200 MHz系统时钟时可以实时解码H.264 High 44 4 profile 4.0 level码流.     

AVS高清视频变长码解码器算法与电路实现

提出一种适用于AVS高清视频解码的变长码解码结构.该结构在一个周期内完成一个指数哥伦布码的解码、查表、语法元素计算和更新码表的操作;通过组合逻辑映射查表,完全避免了对存储器的访问,大大减少面积;采用流水线技术计算输出结果,提高系统性能.对该模块进行了仿真和综合,在0.18μm工艺下,频率为176MHz,面积为8k等效逻辑门.     

基于以太网的嵌入式实时MPEG-2传输系统

介绍了一种实时MPEG-2以太网传输系统的设计方案,它由硬件MPEG-2编/解码器VW2010和基于ARM处理器的嵌入式系统卡构成,前者用于视音频的实时压缩编码和解码,后者将MPEG-2数据流进行IP封装和解封装;还分析了IP网络传输对接收端MPEG-2解码视音频的影响.     

嵌入式实时MPEG-2以太网传输系统的设计

介绍了一种实时MPEG-2以太网传输系统的设计方案,它由硬件MPEG-2编/解码卡和基于ARM处理器的嵌入式系统卡构成,前者用于视音频的实时压缩编码和解码,后者将MPEG-2数据流进行IP封装和解封装,还分析了IP网络传输对接收端MPEG-2解码视音频的影响,并设计了一些测评方法对系统进行了相关测评.     

A Cost-Effective Design for MPEG-2 Audio Decoder with Embedded RISC Core

MPEG-2 audio decoding algorithms are involved of several complex coding techniques and therefore difficult to be implemented by an efficient dedicated architecture design. In this paper, we present an effective architecture for the MPEG-2 audio decoder. The MPEG-2 audio algorithms can be roughly divided into two types of operations. The first type is regular but computation-intensive such as filtering, matrixing, degrouping, and transformation operations. The second type is not regular but computation-intensive such as parsing bitstream, setting operation mode and controlling of all system operations. A RISC core with variable instruction length is designed for the decision-making part, and the dedicated hardware such as special divider, and synthesis filterbank is designed for the computation-intensive part. Based on the standard cell design technique, the VLSI chip consists of 27000 gate counts with the chip size of 6.4 × 6.4 mm². The chip can run at maximum 43.5 MHz clock rate, with the power dissipation of 150 mW at 3 V power supply.     

Evaluating SoC Network Performance in MPEG-4 Encoder

This paper shows how a bus topology performs as a System-on-Chip (SoC) interconnection. We measure and analyze Heterogeneous IP Block Interconnection (HIBI) bus for a multiple clock domain, Multiprocessor System-on-Chip (MPSoC) with an MPEG-4 video encoding application on FPGA. The studied MPSoC contains up to 22 IP blocks: 11 soft processors, 8 hardware accelerators and three other components. A novel approach of frequency scaling is used to isolate the impact of various architecture components. The system is benchmarked in various configurations. For example, HIBI is run at 100× speed with respect to processors to resemble ideal interconnection. Based on the measurements with up to 16.9frames/s CIF (352 × 288) encoding speed, estimation for HDTV resolution video encoder is presented. The required optimizations are discussed. Finally, it is shown that 25frames/s 1280 × 720 video encoder needs 55 MHz HIBI but 670 MHz general-purpose soft RISC processors. In practice, the processing performance has to be boosted by implementing hardware acceleration and improving memory hierarchy. Clearly, HIBI is not the limiting factor.     

MPEG-2音频压缩编码的一种快速算法

采用一片美国TI公司的数字信号处理芯片TMS320C31实现了MPEG-2音频Layer-1、2实时压缩编解码器。为了达到实时的目的,对ISO／IEC 11172-3建议的子带分析方案提出了一种新的快速算法。采用该快速算法,可以使子带分析的运算量降低5倍。仿真实验表明,采用快速算法后,用一片TMS320C31可以达到实时编码。     

MPEG digital audio coding

The Moving Pictures Expert Group (MPEG) within the International Organization of Standardization (ISO) has developed a series of audio-visual standards known as MFEG-1 and MPEG-2. These audio-coding standards are the first international standards in the field of high-quality digital audio compression. MPEG-1 covers coding of stereophonic audio signals at high sampling rates aiming at transparent quality, whereas MPEG-2 also offers stereophonic audio coding at lower sampling rates. In addition, MPEG-2 introduces multichannel coding with and without backwards compatibility to MPEG-1 to provide an improved acoustical image for audio-only applications and for enhanced television and video-conferencing systems. MPEG-2 audio coding without backwards compatibility, called IMPEG-2 Advanced Audio Coding (AAC), offers the highest compression rates. Typical application areas for MPEG-based digital audio are in the fields of audio production, program distribution and exchange, digital sound broadcasting, digital storage, and various multimedia applications. We describe in some detail the key technologies and main features of MPEG-1 and MPEG-2 audio coders. We also present the MPEG-4 standard and discuss some of the typical applications for MPEG audio compression     

基于Nios Ⅱ的数字音频自动增益控制系统

目前国内大多数数字处理实时系统采用ARM或者DSP为核心处理器件结构,存在结构复杂、成本高的缺点。通过对数字音频研究,提出了数字音频的自动增益控制系统的方案。定制了以NiosⅡ为核心的处理器,移植了μC／OSⅡ实时操作系统,设计了数字音频采集IP核,采用3电平法,实现了具有静音处理功能的数字音频信号的自动增益控制系统。实验结果表明：系统体积小、功耗低、实时性强,可广泛应用于数字电视和数字音频播放当中。     

应用于音频芯片的高精度ΣΔ调制器设计

低阶单比特量化ΣΔ调制器简单稳定且特别适用于音频领域的模数转换器。提出了一款应用于音频芯片的二阶单比特量化ΣΔ调制器,利用Simulink对调制器进行建模并确定调制器参数与电路子模块指标。该调制器电路采用CSMC0.35μmCMOS工艺实现,工作的电源电压为5V,采用全差分开关电容技术,功耗为12mW,核心面积为390μm×190μm。在采样频率为12MHz、输入信号频率为20kHz时,调制器精度达到16bit,测试结果验证了设计技术和建模方法。     

MPEG-2 AAC 5.1-Channel Decoder Software for a Low-Power Embedded RISC Microprocessor

Presented here is MPEG-2 AAC low complexity profile decoder software for a low-power embedded RISC microprocessor, NEC V830 (300 mW @133 MHz). Fast processing methods for IMDCT reduce execution time by 41% and help achieve real-time decoding of a 5.1-channel audio signal, while using only 64.7% of processor capacity.     

MPEG-4 natural audio coding

MPEG-4 audio represents a new kind of audio coding standard. Unlike its predecessors, MPEG-1 and MPEG-2 high-quality audio coding, and unlike the speech coding standards which have been completed by the ITU-T, it describes not a single or small set of highly efficient compression schemes but a complete toolbox to do everything from low bit-rate speech coding to high-quality audio coding or music synthesis. The natural coding part within MPEG-4 audio describes traditional type speech and high-quality audio coding algorithms and their combination to enable new functionalities like scalability (hierarchical coding) across the boundaries of coding algorithms. This paper gives an overview of the basic algorithms and how they can be combined.