A new swarm-SVM-based fault diagnosis approach for switched current circuit by using kurtosis and entropy as a preprocessor

This paper presents a new fault diagnosis method for switched current (SI) circuits. The kurtoses and entropies of the signals are calculated by extracting the original signals from the output terminals of the circuit. Support vector machine (SVM) is introduced for fault diagnosis using the entropies and kurtoses as inputs. In this technique, a particle swarm optimization is proposed to optimize the SVM to diagnose switched current circuits. The proposed method can identify faulty components in switched current circuit. A low-pass SI filter circuit has been used as test beached to verify the effectiveness of the proposed method. The accuracy of fault recognition achieved is about 97 % although there are some overlapping data when tolerance is considered. A comparison of our work with Long et al. (Analog Integr Circuit Signal Process 66:93–102, 2011), which only used entropy as a preprocessor, reveals that our method performs well in the part of fault diagnostic accuracy.     

A new switched current circuit fault diagnosis approach based on pseudorandom test and preprocess by using entropy and Haar wavelet transform

This paper presents a new switched current (SI) circuit fault diagnosis approach based on pseudorandom test and preprocess by using entropy and Haar wavelet transform. The proposed method has the capability to detect and identify faulty transistors in SI circuit by analyzing its time response. The use of pseudorandom sequences as a stimulate signal to SI circuit reduces the cost of testing and the overhead of the test generation circuit, and using entropy and Haar wavelet transform to preprocess the time response for feature extraction drastically improves the fault diagnosis efficiency. For both actual experiment and analysis of switched current filters in Z transform (ASIZ) simulation, a low-pass, a band-pass SI filter and a clock feed-through cancellation circuit have been used as test examples to verify the effectiveness of the proposed method. The result shows that the accuracy of fault recognition achieved is about 100% by analyzing low-frequency approximations entropy and high-frequency details entropy. Therefore, it indicates that the presented method is superior than other methods.     

Testing of RF mixers with adaptive filters

This work describes a technique for testing RF mixers with digital adaptive filters. RF circuits are widely used on data transmission applications, such as wireless communication, radio and portable phone systems. However, traditional analog testing covers mainly linear circuits, being not suitable to non-linear pieces of hardware like analog mixers. Herein, an adaptive non-linear filter is trained so that it can mimic the behavior of a RF mixer. Then, a test stimulus is simultaneously applied to the filter and the mixer and the outputs of both circuits are compared to check whether the circuit under test is faulty or fault free. A prototype of a mixer was built in order to allow fault injection in the circuit under test. Thus, the detection capability of the proposed technique could be checked in a real life circuit. The preliminary results point to a very promising test technique. The test is very precise, low cost and allows a complete fault coverage with a very small testing time.     

Fault dictionary based switched current circuit fault diagnosis using entropy as a preprocessor

A novel method based on a fault dictionary that uses entropy as a preprocessor to diagnose faulty behavior in switched current (SI) circuit is presented in the paper. The proposed method uses a data acquisition board to extract the original signal form the output terminals of the circuit-under-tests. These original data are fed to the preprocessors for feature extraction and finds out the entropies of the signals which are a quantitative measure of the information contained in the signals. The proposed method has the capability to detect and identify faulty transistors in SI circuit by analyzing its output signals with high accuracy. Using entropy of signals to preprocess the circuit response drastically reduces the size of fault dictionary, minimizing fault detect time and simplifying fault dictionary architecture. The result from our examples showed that entropies of the signals fall on different range when the faulty transistors^` Transconductance G_m value varying within their tolerances of 5 or 10%, thus we can identify the faulty transistors correctly when the response do not overlap. The average accuracy of fault recognition achieved is more than 95% although there are some overlapping data when tolerance is considered. The method can classify not only parametric faults but also catastrophic faults. It is applicable to analog circuits as well as SI ones. A low-pass and a band-pass SI filter and a Clock feedthrough cancellation circuit have been used as test beached to verify the effectiveness of the proposed method. A comparison of our work with Yuan et al. (IEEE Trans Instrum Meas 59(3):586–595, 2010), which used entropy and kurtosis as preprocessors, reveals that our method requiring one feature parameter reduces the computation and fault diagnosis time.     

OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.     

Fault Detection of Analog Circuits Using Network Parameters

A new method to detect component faults in analog circuits is proposed in this paper. Network parameters like driving point impedance, transfer impedance, voltage gain and current gain are used to detect component faults in analog circuits as these network parameters are sensitive to the components of the circuit. Using montecarlo simulation each component of the circuit is varied within its tolerance limit and the minimum and the maximum values of each network parameter are found for fault free circuit. At the time of testing, the network parameters are found for the injected fault and if any one or more network parameters is exceeding its predetermined bound limits then the circuit is confirmed faulty. The proposed method is validated through second order Sallenkey band pass filter and fourth order Chebyshev low pass filter circuits. Numerical results are presented to clarify the proposed method and prove its efficiency.     

High-speed switched-current matched filter for WCDMA receivers

A matched filter (MF) based upon the cascoded class AB SI technique is presented for spread-spectrum communication receivers. Accomplished through both architectural and circuit developments, the filter's features include low power, high speed and compatibility with standard CMOS process inherent to SI signal processing. For performance assessment, a 31-tap 80 MS/s SI MF for despreading task in future high-speed WCDMA receivers is demonstrated.     

Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits

A new neural network-based analog fault diagnosis strategy is introduced. Ensemble of neural networks is constructed and trained for efficient and accurate fault classification of the circuit under test (CUT). In the testing phase, the outputs of the individual ensemble members are combined to isolate the actual CUT fault. Prominent techniques for producing the ensemble are utilized, analyzed and compared. The created ensemble exhibit high classification accuracy even if the CUT has overlapping fault classes which cannot be isolated using a unitary neural network. Each neural classifier of the ensemble focuses on a particular region in the CUT measurement space. As a result, significantly better generalization performance is achieved by the ensemble as compared to any of its individual neural nets. Moreover, the selection of the proper architecture of the neural classifiers is simplified. Experimental results demonstrate the superior performance of the developed approach.     

A simple structure wavelet transform circuit employing function link neural networks and SI filters

Signal processing by means of analog circuits offers advantages from a power consumption viewpoint. Implementing wavelet transform (WT) using analog circuits is of great interest when low-power consumption becomes an important issue. In this article, a novel simple structure WT circuit in analog domain is presented by employing functional link neural network (FLNN) and switched-current (SI) filters. First, the wavelet base is approximated using FLNN algorithms for giving a filter transfer function that is suitable for simple structure WT circuit implementation. Next, the WT circuit is constructed with the wavelet filter bank, whose impulse response is the approximated wavelet and its dilations. The filter design that follows is based on a follow-the-leader feedback (FLF) structure with multiple output bilinear SI integrators and current mirrors as the main building blocks. SI filter is well suited for this application since the dilation constant across different scales of the transform can be precisely implemented and controlled by the clock frequency of the circuit with the same system architecture. Finally, to illustrate the design procedure, a seventh-order FLNN-approximated Gaussian wavelet is implemented as an example. Simulations have successfully verified that the designed simple structure WT circuit has low sensitivity, low-power consumption and litter effect to the imperfections.     

Analog Circuits Fault Detection Using Cross-Entropy Approach

This paper presents a novel method that can detect component faults in analog circuits. Because the probability density function (PDF) of output voltage (current) is sensitive to the components of the circuit, the cross-entropy between the good circuit and the bad circuit is employed to detect component faults in analog circuits based on the autoregressive (AR) model. In the proposed approach, the value of each component of the circuit undertest (CUT) is varied within its tolerance limit using Monte Carlo simulation. The minimal and maximal bounds of the cross-entropy are found for fault-free circuit. While testing, the cross-entropy is obtained. If cross-entropy lies outside the tolerance limit then the CUT is declared faulty. The effectiveness of the proposed method is demonstrated via the second order Sallenkey bandpass filter circuit and continuous-time low pass state-variable filter circuit.     

Fault detection in analog and mixed-signal circuits by using Hilbert–Huang transform and coherence analysis

Using Hilbert–Huang transform (HHT) and coherence analysis, a signature extraction method for testing analog and mixed-signal circuits is proposed in this paper. The instantaneous time–frequency signatures extracted with HHT technique from the measured signal of circuits under test (CUT) are used for faults detection that is implemented through comparing the signatures of faulty circuits with that of the fault-free circuit. The coherence functions of the instantaneous time–frequency signatures and its integral help to test faults in the faulty dictionary according to the minimum distance criterion. The superior capability of HHT-based technique, compared to traditional linear techniques such as the wavelet transform and the fast Fourier transform, is to obtain the subtle time-varying signatures, i.e., the instantaneous time–frequency signatures, and is demonstrated by applying to Leapfrog filter, a benchmark circuit for analog and mixed-signal testing, with 100% of F.D.R (fault detection rate) in the best cases and with the least 24.2% of F.L.R. (fault localization rate) with one signature.     

Analog Fault Diagnosis Using Conic Optimization and Ellipsoidal Classifiers

This paper introduces a new fault diagnosis strategy for analog circuits based on conic optimization and ellipsoidal classifiers. Ellipsoidal classifiers are trained for efficient and accurate fault classification of the circuit under test (CUT). In the testing phase, the output of the ellipsoidal classifiers is used to isolate the actual CUT fault. The constructed classifiers exhibit high classification rate with competitive computational complexity even if the CUT has overlapping faults. Experimental results demonstrate the superior performance of the ellipsoidal classifiers in analog fault diagnosis.     

Reducing Test Time in the High-Volume Production of Analog Circuits using Efficient Test-Vector Generation and Interpolation Techniques

Test cost is one of the main factors determining the profit margin of a device in production. Current test strategies require hundreds of measurements to determine the specifications of a parameter. In this paper, we present an automatic test-vector generation technique that is based on transfer function manipulation and requires only one circuit simulation. The proposed method consists of generating the first set of vectors by applying a derivation technique to the golden transfer function of the circuit under test (CUT). An interpolation technique allows a new transfer function to be constructed based on the first set of test vectors. The difference between the reconstructed transfer function and the golden transfer function is used to select the second set of test vectors. These new test vectors are selected to achieve the best possible fit. Our technique reduces the test vector size to values that at present can be achieved only by using powerful and time-consuming fault simulation tools. As an example, we apply the method to state variable and Chebyshev filters. We also compute the fault coverage in order to demonstrate the effectiveness of this new technique.     

Automated design of switched-current filters

This paper describes the automated design and synthesis of switched-current (SI) filters using SCADS, a flexible CAD system integrated in a major VLSI design suite. With this system, the nonspecialist can produce high performance analog filters suitable for mixed signal CMOS IC's fabricated using only standard digital processes. To achieve high levels of performance on silicon, filter designs are realized using an enhanced differential circuit technique (S²I) in its integrators and sample-and-hold cells. The design system is described in terms of the embedded circuits, its integrated tool set, the filter design flow and the engineering procedures for ensuring reliable circuit operation. Examples of high performance video frequency filters are presented, each generated automatically by SCADS within one day. Fabricated in a 0.8 μm standard CMOS process, they demonstrate state-of-the-art performance     

A test methodology for finite state machines using partial scan design

This paper presents an efficient automatic test pattern generation technique for loop-free circuits. A partial scan technique is used to convert a sequential circuit (finite state machine) with arbitrary feedback paths into a pipelined circuit for testing. Test generation for these modified circuits can be performed with a modified combinational automatic test pattern generator (ATPG), which is much faster than a sequential ATPG. A combinational model is obtained by replacing all flipflops by buffers. It is shown that a test vector for a fault in this model obtained by a combinational test generator can be expanded into a sequence of identical vectors to detect the same fault in the original sequential circuit. This technique may abort a few faults which can then be resolved with a sequential ATPG. Experiments on the ISCAS89 circuits show that only 30% to 70% of flipflops require scanning in larger circuits and 96% to 100% fault coverage for almost all the circuits without resorting to a sequential ATPG.This research was sponsored by the Semiconductor Research Corporation, Contract 90-DP-142.     

伪准确计算的高故障容忍度冗余电路实现

本文提出了伪准确计算的概念。集成电路规模的扩大和制造工艺中不断增加的缺陷给大规模集成电路的测试和验证带来巨大的压力。针对故障容忍度（Fault Tolerance,FT）的研究是缓解测试和验证压力的有效方向。传统的错误容忍度的研究和相关的电路设计主要通过冗余的可替换电路实现无错误电路（有时只针对特定目标程序）。本文通过重新定义“准确”,提出了伪准确定义的概念,并通过创新的冗余电路结构实现。示例电路为冗余伪准确反相器。本文通过伪准确反相器与三模冗余（triple-modular redundancy TMR）和双备用（two spares）等FT技术的比较,给出伪准确计算的实现原理、误差积累分析。示例电路的仿真和分析表明伪准确计算在缩减测试成本和提高系统可靠性方面有潜在的价值。     

Fault-based testing and diagnosis of balanced filters

The test and diagnosis of fully differential analogue filters are addressed in this paper. Full coverage of hard/soft faults affecting circuit behaviour can be achieved by adjusting the tolerance window of the built-in self-test circuitry and the amplitude and frequency of the input test signal. Under a single fault assumption, the faulty active or passive component is located and the actual defective value of a faulty passive component is determined. A test generation procedure which results in maximum fault coverage and maximal diagnosis of hard/soft faults in the filter is presented. The test and diagnosis approach can be made compatible with IEEE Std 1149.1 for boundary scan testing.This work is part of AMATIST ESPRIT-III Basic Research Project, funded by CEC under contract #8820.     

Testing of programmable analog neural network chips

Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by National Science Foundation under Grant MIP-8904172.     

An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing

With fabrication technology reaching nano levels, systems are exposed to higher susceptibility to soft errors. Thus, development of effective techniques for designing soft error tolerant systems is of high importance. In this work, an integrated soft error tolerance technique based on logical implications and transistor sizing is proposed. In order to reduce implication learning time, a set of source and target nodes with predefined thresholds are selected and implications between these nodes are extracted. Then, the impact of adding a functionally redundant wire (FRW) due to each implication is evaluated. This is done based on identifying an implication path and the gates along the implication path whose detection probabilities will be reduced due to adding the implication FRW. Then, the gain of an implication is estimated in terms of reduction in fault detection probabilities of gates along an implication path. The implication with the highest gain is selected. The process is repeated until the gain is less than a predetermined threshold. The proposed implication-based fault tolerance technique enhances the circuit reliability with minimal area overhead based on enhancing logical masking. However, its effectiveness depends on the existence of such relations in a circuit and can enhance circuit reliability upto a certain level. To enhance circuit reliability to any required level, selective-transistor redundancy (STR) based technique is then applied. This technique is based on providing fault tolerance for individual transistors with high detection probability based on transistor duplication and sizing. Experimental results show that the proposed integrated fault tolerance technique achieves similar reliability in comparison to applying STR alone with lower area overhead.     

Balance testing and balance-testable design of logic circuits

We propose a low-cost method for testing logic circuits, termed balance testing, which is particularly suited to built-in self testing. Conceptually related to ones counting and syndrome testing, it detects faults by checking the difference between the number of ones and the number of zeros in the test response sequence. A key advantage of balance testing is that the testability of various fault types can be easily analyzed. We present a novel analysis technique which leads to necessary and sufficient conditions for the balance testability of the standard single stuck-line (SSL) faults. This analysis can be easily extended to multiple stuck-line and bridging faults. Balance testing also forms the basis for design for balance testability (DFBT), a systematic DFT technique that achieves full coverage of SSL faults. It places the unit under test in a low-cost framework circuit that guarantees complete balance testability. Unlike most existing DFT techniques, DFBT requires only one additional control input and no redesign of the underlying circuit is necessary. We present experimental results on applying balance testing to the ISCAS 85 benchmark circuits, which show that very high fault coverage is obtained for large circuits even with reduced deterministic test sets. This coverage can always be made 100% either by adding tests or applying DFBT.This research was supported by the National Science Foundation under Grant No. MIP-9200526. Parts of this paper were published in preliminary form in Proc. 23rd Symp. Fault-Tolerant Computing, Toulouse, June 1993, and in Proc. 31st Design Automation Conf, San Diego, June 1994.