Compensation technique for DC and transient instability of thin film transistor circuits for large-area devices

A reliable driving scheme that can compensate for the inherent instability of hydrogenated amorphous silicon (a-Si:H) thin film transistors (TFTs) is essential for implementation of large-area devices including displays and sensor arrays for bio-imaging applications. In particular, for high precision and high-resolution devices, the technique should be accurate and fast. A new driving scheme is presented that enables control of the DC and transient shift in the threshold voltage (V _T ) and gate voltage of drive/amplifier TFT, while fulfilling the timing requirements for the different applications. The transient shift in the gate voltage has been known to contribute as much as 10% error in controlling the DC shift in the V _T whereas it is less than 0.5% for the driving scheme presented here.     

Switched-capacitor DC/DC converters with resonant gate drive

In this paper, we examine how switched-capacitor (SC) converters can be used in low-voltage low-power DC/DC applications with power management. Analysis of losses is presented to facilitate SC converter design and optimization. A resonant gate drive is proposed to reduce switching losses and simplify control of switches in SC converters. A closed-loop controller is designed to enable and disable oscillations of the resonant gate drive so that the output DC voltage is well regulated down to zero load and so that high efficiency is maintained for a very wide range of loads. Results are experimentally verified on two low-power (0.2 and 5 W) five-one step-down converters with regulated 3 Vdc output and efficiency greater than 80% in a 100-1 load range     

A feedback loop regulated bootstrap driver circuit with improved drive capability for high voltage buck DC–DC converter

A novel bootstrap driver circuit applied to high voltage buck DC–DC converter is proposed. The gate driver voltage of the high side switch is regulated by a feedback loop to obtain accurate and stable bootstrapped voltage. The charging current of bootstrap capacitor is provided by the input power of the DC–DC converter directly instead of internal low voltage power source, so larger driver capability of the proposed circuit can be achieved. The bootstrap driver circuit starts to charge the bootstrap capacitor before the switch node SW drop to zero voltage at high-side switch off-time. Thus inadequate bootstrap voltage is avoided. The proposed circuit has been implemented in a high voltage buck DC–DC converter with 0.6 µm 40 V CDMOS process. The experimental results show that the bootstrap driver circuit provides 5 V stable bootstrap voltage with higher drive capability to drive high side switch. The proposed circuit is suitable for high voltage, large current buck DC–DC converter.     

高端MOS管栅极驱动技术研究

高端MOS管驱动电路在高压输入大功率电源中被广泛应用。分析了高端MOS管的驱动原理,对影响高端MOS管驱动的各种因素进行了探讨,提出了适合高端MOS管驱动的基本方法。较全面地评估了传统的变压器驱动电路和自举驱动电路对高端MOS管驱动的影响,继而提出了适合高端MOS管驱动的线路结构,并采用该方案设计了一个实验电路。仿真和实验电路测试结果表明,设计电路满足要求。     

High efficiency, unity power factor VVVF drive system of aninduction motor

A high-efficiency, unity-power-factor VVVF (variable voltage, variable frequency) drive scheme for an induction motor is presented. A unity-power-factor PWM (pulsewidth modulated) converter regulates DC voltage. An inverter circuit with the magnetic flux control PWM method generates VVVF PWM waveforms. The modulation factor of the inverter PWM control with controllable DC link DC voltage is studied. As a result, the distortion factor and the switching frequency are reduced by over-modulation with low DC link voltage. A high-efficiency and unity-power-factor VVVF induction motor drive has been achieved using the control strategy     

Zero-voltage-switched quasi-resonant buck and flybackconverters-experimental results at 10 MHz

Experimental results are presented for buck and flyback zero-voltage-switched (ZVS) quasi-resonant converters (QRCs) operating above 5 MHz. A design procedure for a buck ZVS QRC is proposed that minimizes voltage stress to the power MOSFET transistor while maintaining zero voltage switching for specified ranges of input voltage and load resistance. A quasi-resonant gate drive scheme is also proposed and implemented in a buck converter. The drive is simple and provides high switching speed. Power dissipation in the gate drive is substantially reduced due to the quasi-resonant operation. The ZVS QRC technique described is suitable for very-high-frequency operation due to its ability to reduce dynamic turn-on losses, Miller effect, dv/dt, and di//dt and can be applied in distributed onboard power supplies     

Impact of single pMOSFET dielectric degradation on NAND circuit performance

Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source-to-drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.     

一种测试功率MOSFET热阻的新方法

阐述了一种测试功率MOSFET热阻的新方法。该方法选取漏源电流作为温度敏感参数,在相同漏源电压和栅源电压幅度下,当栅源电压条件由直流形式变为脉冲形式时,漏源电流是有差异的,这一差异是由结温的不同造成的。而脉冲栅源电压下环境温度的调整可以用来模拟直流条件下的结温,由此可以测得器件在直流条件下的热阻。该方法具有精度高、实现容易和操作方便等优点,可作为功率MOS器件结温和热阻的有效测试方法。     

Acoustic-resonance-free electronic ballast for automotive HID lamps

A novel cost-effective and acoustic-resonance-free electronic ballast used to drive automotive high intensity discharging (HID) lamps that utilise a constant lamp power control scheme is proposed. The presented ballast is comprised of a buck-boost flyback converter to provide negative DC voltages and a half-bridge-type inverter to supply the lamp with low-frequency, square-wave AC voltage/ current. Owing to its low-frequency operation, no acoustic resonance occurs on the automotive HID lamps. Design guidelines and experimental results are demonstrated for a 35 Wautomotive HID lamp prototype ballast operating at 400 Hz switching frequency with battery input DC voltage of 12 V.     

Realization of an 850V High Voltage Half Bridge Gate Drive IC with a New NFFP HVI Structure

A NFFP HVI structure which implements high breakdown voltage without using additional FFP and process steps is proposed in this paper. An 850 V high voltage half bridge gate drive IC with the NFFP HVI structure is experimentally realized using a thin epitaxial BCD process. Compared with the MFFP HVI structure, the proposed NFFP HVI structure shows simpler process and lower cost. The high side offset voltage in the half bridge gate drive IC with the NFFP HVI structure is almost as same as that with the self-shielding structure.     

An induction motor drive using an improved high frequency resonantDC link invertor

An induction motor drive that uses an improved high-frequency resonant DC link inverter is presented. The resonant circuit was systematically analyzed first to establish the criteria for initial current selection, and a circuit to establish the bidirectional initial current was then proposed. The proposed current initialization scheme solves voltage overshoot and zero crossing failure problems in the ordinary resonant DC link inverters. A three-phase 3 kW insulated-gate-bipolar-transistor (IGBT) based 60 kHz resonant link inverter has been constructed and successfully tested with an induction motor drive. The speed control system is implemented using two microprocessors. Experimental results are presented to show superior operation of the proposed resonant DC link inverter drive     

截止频率53GHz的高性能0.18μm射频nMOSFET

阐述了0.18μm射频nMOSFET的制造和性能.器件采用氮化栅氧化层/多晶栅结构、轻掺杂源漏浅延伸结、倒退的沟道掺杂分布和叉指栅结构.除0.18μm的栅线条采用电子束直写技术外,其他结构均通过常规的半导体制造设备实现.按照简洁的工艺流程制备了器件,获得了优良的直流和射频性能:阈值电压0.52V,亚阈值斜率80mV/dec,漏致势垒降低因子69mV/V,截止电流0.5nA/μm,饱和驱动电流458μA/μm,饱和跨导212μS/μm(6nm氧化层,3V驱动电压)及截止频率53GHz.     

A new gate drive circuit for high-speed operation of GTO thyristors

This paper presents a new gate turn-off drive circuit for GTO thyristors, which can accomplish faster turn-off switching for high-speed operation of the GTO. The switching characteristics of GTO's can be improved by use of the gate drive circuit that is able to make a very high rate of the negative gate current. The major disadvantage of the conventional gate turn-off driving technique is that it has a difficulty in realizing higher negative di_G/dt due to the maximum reverse gate-cathode voltage and the stray inductances within the gate turn-off drive circuit. This paper shows that this problem can be overcome by adding another gate turn-off drive circuit to the conventional gate turn-off drive circuit. Simulation and experimental results in conjunction with chopper circuit verify the performance of the proposed gate drive circuit     

A novel 4H-SiC MESFET by lateral insulator region to improve the DC and RF characteristics

In this paper, a novel recessed gate metal–semiconductor field-effect transistor (RG-MESFET) is presented by modifying the depletion region and the electric field. The proposed structure improves the breakdown voltage, drain current and high frequency characteristics by embedding a lateral insulator region between drain and gate while is placed laterally into the metal gate and a silicon well exactly under the insulator region. We called this new structure as modified recess gate MESFET (MRG-MESFET). The radio frequency and direct current (DC) characteristics of the proposed structure is studied using numerical simulations and compared with a conventional MESFET (C-MESFET). The breakdown voltage, drain current DC transconductance and maximum power density of the proposed structure increase by 27%, 16.5%, 15% and 48%, respectively, relative to the C-MESFET. Also, the gate-source capacitance and the minimum noise figure of the proposed structure improve relative to the C-MESFET. The proposed structure can be used for high breakdown voltage, high saturation drain current, high DC transconductance, high power, high frequency, and low noise applications.     

基于薄外延技术的高压BCD兼容工艺

针对高压应用领域,开发了一种基于薄外延技术的高压BCD兼容工艺,实现了900V高压双RESURF LDMOS与低压CMOS,BJT器件的单片集成.与传统厚外延技术相比,工艺中n型外延层的厚度减小为9μm,因此形成pn结对通隔离的扩散处理时间被极大减小,结隔离有更小的横向扩散,节约了芯片面积,并改善了工艺的兼容性.应用此单层多晶、单层金属高压BCD兼容工艺,成功研制出一种基于耦合式电平位移结构的高压半桥栅极驱动电路,电路高端浮动偏置电压为880V.     

Separation of interface and nonuniform oxide traps by the DCcurrent-voltage method

Areally nonuniform distribution of oxide charge gives a significant distortion in the gate capacitance and subthreshold DC drain current versus DC gate voltage characteristics. This distortion prevents a reliable determination of the spatial profile of interface and oxide traps generated when a MOS transistor is subjected to channel hot carrier stress. A new procedure is demonstrated which separates the nonuniform oxide charge distribution from interface traps by combining the analysis of two experimental DC characteristics: the subthreshold drain-current and the DC base recombination current versus the gate voltage     

Stacked PMOS clamps for high voltage power supply protection

Large p-channel MOS (PMOS) field-effect transistors (FETs) with multiple gates can be arranged to provide ESD protection to high voltage on-chip power supplies in submicron integrated circuits. These clamps divide the supply voltage among several gate oxides; the circuitry accompanying the large series FETs provides near-maximum gate drive during the ESD for high pulsed current. Layouts are densely packed because minimum dimensions can be used and because no contact is needed between the stacked gates. The designs for high voltage are extensions of the large PMOS FET ESD clamps and timed drive circuitry that are used to clamp ordinary on-chip power supply lines.     

GaN功率器件栅驱动电路技术综述

第三代宽禁带半导体GaN晶体管具有低导通阻抗、低寄生参数和更快的开关速度,有望取代传统Si MOSFET,成为未来高性能电源系统实现方案。GaN器件的优势在400 V以上高压系统中更为明显,可以实现更高的开关频率和功率密度,显著提高系统的转换效率,特别适合电源模块小型化发展趋势。介绍了200 V以下低压GaN驱动电路的应用和关键技术。分析了从低压系统拓展到400 V以上高压系统时需要作出的优化与改进。详细介绍了高压GaN系统中基于无磁芯变压器耦合隔离的隔离驱动技术和耗尽型GaN负压栅驱动技术。最后,总结了目前高压GaN驱动电路在工业领域的具体应用。     

A new topology for unipolar brushless DC motor drive with high power factor

A new converter topology is proposed for driving a permanent magnet brushless DC (BLDC) motor with unipolar currents. It is based on a front-end single-ended primary inductance converter (SEPIC) and a switch in series with each phase. All the switches are ground-referenced, which simplifies their gate drives. The available input voltage can be boosted for better current regulation, which is an advantage for low voltage applications. For operation with an AC supply, the SEPIC converter is designed to operate in the discontinuous conduction mode. In this operation mode, it approximates a voltage follower and the line current follows the line voltage waveform to a certain extent. The reduction in low-order harmonics and improved power factor is achieved without the use of any voltage or current sensors. The simplicity and reduced parts count of the proposed topology make it an attractive low-cost choice for many variable speed drive applications.     

高温CMOS数字集成电路直流传输特性的分析

分析了高温CMOS倒相器和门电路的直流传输特性,建立了相应的解析模型。根据分析,高温MOSFET阈值电压和载流子迁移率的降低,以及MOSFET漏端pn结泄漏电流的增加引起了CMOS倒相器和门电路直流传输特性劣化。在MOSFET漏端pn结泄漏电流的影响下,高温CMOS倒相器和门电路的输出高电平下降,低电平上升,导致了电路的功能失效。给出的理论模型和实验结果一致。