NOC路由节点VLSI设计

基于wormhole交换策略和目的地址确定性路由算法,采用三级流水线的结构实现了片上网络中的路由节点.该路由节点适用于Mesh和Torus拓扑,并采用虚通道技术增加吞吐量.在Xilinx的FPGA上实现后可知,该路由节点最高可工作在130MHz的时钟频率上,传输带宽为20.8Gb/s.     

一种分层结构的片上网络路由设计

随着同一芯片中处理器数日的不断增加,层次化网络结构将成为片上网络(NoC)拓扑研究的热点.针对典型的NoC不规则分层拓扑结构,设计了一套新的免死锁混合路由算法以及新的节点编址方式.同时提出了一种新的交换节点设计构想,并给出了一种有效的拥塞控制策略.仿真结果表明,当网络中数据流量变大时分层网络比传统二维网络具有更小的传输时延以及更大的吞吐量.     

Torus网络中基于中心距离的完全自适应路由算法

Torus网络凭借其优越的结构特性,引起了工业界和学术界的广泛关注.高效、无死锁的路由算法设计是互连网络研究的一个重要方面.针对Torus网络实现自适应路由所需虚通道数目多的缺点,提出了自适应路由算法Gear,该算法基于中心距离的方法来限制虚通道的使用,在虚切通交换下仅需两条虚通道即可为Torus网络提供无死锁自适应路由.通过仿真对所提算法的有效性进行了验证,结果表明,在同等情况下算法Gear的性能较经典的维序路由和Duato协议具有非常明显的优势.     

基于二维torus片上网络的间隙式流量控制及路由算法的研究

基于片上网络中常用的虚切通交换技术,提出了间隙式流量控制策略,为了改进片上网络路由机制的免死锁性和减少数据包的传输路径,根据二维Torus片上网络结构,又研究了与此相对应的间隙式自适应路由算法,并对该算法进行了免死锁证明.在NOXIM下仿真结果表明,此算法在数据包延迟和系统吞吐量方面明显优于X-Y,West-First,Odd-Even这些常规的路由算法.     

连接主从IP核的Octagon环形网络拓扑结构

本文提出了一种连接主从IP核的Octagon环型(Master-Slave IP Core connected Octagon Loop,MSOL)拓扑结构,该拓扑结构具有8m个节点,并且每个节点分别连接主从IP核,除外层环上各核连接3个相邻节点外,内层环上各节点均与4个相邻节点连接。MSOL是一种拓扑结构简单、平面的、对称的并且具有良好扩展性的互连网络,采用基于最短路径的路由算法,在仿真实验中,对MSOL,Mesh和Cluster-Mesh网络的平均通讯延迟和平均吞吐量进行了模拟分析,结果表明MSOL互连网络较好的平衡了网络性能和成本,是一种更为优化、高效的片上网络拓扑结构。     

WSN中基于能量感知的最小跳数路由算法

无线传感器网络的拓扑往往由于节点死亡而发生变化。网络拓扑的重新构建加速了剩余传感器节点的死亡,缩短了网络的生存时间。针对无线传感器网络对网络生存时间的苛刻要求,提出了一种基于能量感知的最小跳数路由算法。建立路由时,该算法综合考虑了节点剩余能量和该节点潜在的转发能力。仿真结果显示,该算法在生存时间、存活节点数和吞吐量方面的性能要远优于LEACH算法和HEED算法。     

AODV路由协议的改进算法

无线Ad hoc网络拓扑结构动态变化的特点,决定了路径断裂是不可避免的。路径断裂会引起源节点路由重建,源节点频繁地发起路由重建过程会降低网络的性能。AODV协议中采用本地修复机制来减少源节点路由重建的次数。基于这一思想,文章提出了一种AODV路由协议改进算法SRP,旨在进一步提高本地修复的成功率。仿真结果表明,在拓扑结构变化迅速的Ad hoc网络中,SRP协议比AODV路由协议有更好的网络性能。     

基于路由考虑的人群网络分类探索

人群网络是一种特殊的容迟网络。在这种网络中,人通过携带随身移动通信设备,利用短距离无线电进行通信。对于这种网络路由算法的研究,一个关键的方向就是研究设备的载体--人群网络的拓扑结构特点。由于人的移动性导致网络拓扑结构不断变化,一个特定的路由算法很难一直保持好的性能。因此,为了能更好的进行路由算法设计,提出对人群网络拓扑结构变化进行分类。     

一种分布式无线网络自适应拓扑抗毁性优化机制

分布式无线网络的抗毁性能受网络拓扑结构的直接影响,优化拓扑结构是提升网络抗毁性的重要手段。基于此,提出了一种不依赖于全网拓扑信息获取的分布式自适应网络拓扑优化机制,并设计了启发式算法。算法设计基于对局部k跳邻域网络拓扑的代数连通度分析,自适应选取对局部网络拓扑连通性影响最小的冗余节点,并执行冗余节点的小范围移动部署,优化网络拓扑结构,实现网络拓扑代数连通度的提升。最后,通过仿真实验验证了算法能够有效提升网络的抗毁性。     

一种主动均衡节点能耗的无线传感器网络拓扑控制算法

无线传感器网络中网络拓扑的动态调整对于提高路由协议和MAC协议的效率,延长网络的生存期,提高网络通信效率等方面具有重要的作用.本文在分析了一些拓扑控制算法的基础上,提出了一种新的层次型拓扑生成算法,该算法引入了时间门限值和节点剩余能量两个参数,在解决能耗不均衡问题上采取相对主动的方法.能够有效地均衡网络节点的能耗并延长网络的生存周期.     

An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture

This paper presents an Enhanced Clustered Mesh (EnMesh) topology for a Network-on-Chip architecture in order to reduce the communication delay between remote regions by considering the physical positions of remote nodes. EnMesh topology includes short paths between diagonal regions to ensure fast communication among remote nodes. The performance and silicon area overhead of EnMesh are analyzed and compared to those of state-of-the-art topologies such as Mesh, Torus, and Butterfly-Fat-Tree (BFT). Experimental results demonstrate that EnMesh outperforms other existing regular topologies in terms of throughput, latency, packet loss rate, and silicon area overhead.     

片上网络路由技术研究

片上网络满足了大规模集成电路发展对扩展性、能耗、面积、时钟异步、重用性等方面的需求,是对原有设计方法的一次革新。文中研究了片上网络的一项关键技术——路由技术。对其相关的包交换技术、虚拟通道技术和死锁避免技术进行了详细的分析介绍和优缺点的比较,给出了有益于片上网络沿用的结论。     

无线NoC研究与进展

分析了无线NoC的一般结构,对两种典型拓扑结构及其相关特性进行了比较,并对无线NoC涉及到的关键通信机制,特别是片上天线、路由及通信协议对其性能的影响进行了讨论,最后对未来无线NoC的技术热点及难点问题进行了总结和展望。     

基于内建自测技术的Mesh结构NoC无虚通道容错路由算法

 在Zhang's算法绕行思想的基础上,提出了一种2D-Mesh结构片上网络无虚通道容错路由算法,用于解决多故障节点情况下片上网络的无虚通道容错路由问题.算法利用内建自测试机制获取故障区域的位置信息,通过优化绕行策略来均衡故障区域周围链路的负载并减少部分数据的绕行距离.针对8×8的2D-Mesh网络的仿真表明,与Chen's算法相比,在故障区域大小为2×2,网络时延为70 cycles的情况下,随着故障区域位置的变化所提算法可提高1.2%到4.8%的网络注入率.且随着故障区域面积的扩大,所提算法在减少通信时延,提高网络吞吐量方面的作用更为明显.     

基于片上网络的系统芯片测试研究

文章介绍了基于片上网络对系统芯片进行测试的原理和实例，这是一种新的设计方法。首先讨论了未来系统芯片存在的各方面测试挑战，并提出了基于片上网络结构的解决方案。其次，在OSI网络堆栈参考模型的基础上．提出了面向测试的片上网络协议堆栈以及对应的测试服务。最后，介绍了基于片上网络的模块化测试方法。     

S-Mesh: a Mesh-based on-chip network with separation of control and transmission

The current network-on-chip (NoC) topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestion control and properties of an NoC system. Therefore, these make switch architecture far more complex. This article puts forward a separating on-chip network architecture based on Mesh (S-Mesh). S-Mesh is an on-chip network that separates routing decision flow from the switches. It consists of two types of networks: datapath network (DN) and control network (CN). The CN establishes data paths for data transferring in DN. Meanwhile, the CN also transfers instructions between different resources. This property makes switch architecture simple, and eliminates conflicts in network interface units between the resource and switch. Compared with 2D-Mesh, Torus Mesh, Fat-tree and Butterfly, the average packet latency in S-Mesh is the shortest when the packet length is more than 53 B. Compared with 2D-Mesh, the areas savings of S-Mesh is about 3%--7%, and the power dissipation is decreased by approximate 2%.     

基于拓扑划分的片上网络快速映射算法

该文针对片上网络建立了以能耗和流量均衡为优化目标的映射模型,提出一种基于拓扑划分的快速映射算法(TPBMAP)。该算法不仅考虑芯片的布局特性从而产生规整的拓扑,还采用虚拟IP核技术修正通信核图以完成IP核和网络节点数不等的映射;通过引入以流量均衡为目标的优化模型同时将通信量大的IP核映射到拓扑边缘区域,有效地降低了网络中心的流量;采用迭代的拓扑划分方法以及将通信量大的IP核映射到网络相邻位置,可快速完成低能耗映射。仿真结果表明,相比现有算法,该文提出的算法在映射速度、全网能耗以及网络中心流量等方面有较大优势。     

SRNoC: A novel high performance Shared-Resource routing scheme for Network-on-Chip

This paper proposes a novel Shared-Resource routing scheme, SRNoC, that not only enhances network transmission performance, but also provides a high efficient load-balance solution for NoC design. The proposed SRNoC scheme expands the NoC design space and provides a novel effective NoC framework. SRNoC scheme mainly consists of the topology and routing algorithm. The proposed topology of SRNoC is based on the Shared-Resource mechanism, in which the routers are divided into groups and each group of routers share a set of specified link resource. Because of the usage of Shared Resource mechanism, SRNoC could effectively distribute the workload uniformly onto the network so as to improve the utilization of the resource and alleviate the network congestion. The proposed routing algorithm is a minimal oblivious routing algorithm. It could improve average latency and saturation load owing to its flexibility and high efficiency. In order to evaluate the load-balance property of the network, we proposed a method to calculate the Φ which represents the characteristic value of load-balance. The smaller the Φ, the better the performance in load-balance. Simulation results show that the average latency and saturation load are dramatically improved by SRNoC both in synthetic traffic patterns and real application traffic trace with negligible hardware overhead. Under the same simulation condition, SRNoC could cut down the total network workload to 48.67% at least. Moreover, SRNoC reduces the value of Φ 45% at least compared with other routing algorithms, which means it achieves better load-balance feature.     

Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique

The network-on-chip (NoC) design problem requires the generation of a power and resource efficient interconnection architecture that can support the communication requirements for the SoC with the desired performance. This paper presents a genetic algorithm-based automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. The technique operates on the system-level floorplan of the system on chip (SoC) and accounts for the power consumption in the physical links and the routers. The design technique solves a multi-objective problem of minimizing the power consumption and the router resources. It generates a Pareto curve of the solution set, such that each point in the curve represents a tradeoff between power consumption and associated number of NoC routers. The performance and quality of solutions produced by the technique are evaluated by experimentation with benchmark applications and comparisons with existing approaches.     

Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures

Modern iterative channel code decoder architectures have tight constrains on the throughput but require flexibility to support different modes and standards. Unfortunately, flexibility often comes at the expense of increasing the number of clock cycles required to complete the decoding of a data-frame, thus reducing the sustained throughput. The Network-on-Chip (NoC) paradigm is an interesting option to achieve flexibility, but several design choices, including the topology and the routing algorithm, can affect the decoder throughput. In this work logarithmic diameter topologies, in particular generalized de-Bruijn and Kautz topologies, are addressed as possible solutions to achieve both flexible and high throughput architectures for iterative channel code decoding. In particular, this work shows that the optimal shortest-path routing algorithm for these topologies, that is still available in the open literature, can be efficiently implemented resorting to a very simple circuit. Experimental results show that the proposed architecture features a reduction of about 14% and 10% for area and power consumption respectively, with respect to a previous shortest-path routing-table-based design.