The turn-on delay time of silicon p-n-p-n switches

The turn-on delay time of silicon p-n-p-n switches has been experimentally shown to be inversely proportional to gate currents in excess of the threshold value. Based on the measurements of bidirectional p-n-p-n switches, it is demonstrated that p-n-p-n structures with remote gating have inherently longer turn-on delay times than those of the conventional construction having the gate lead attached to a base region.     

Modeling the positive-feedback regenerative process of CMOS latchupby a positive transient pole method. I. theoretical derivation

A novel method to characterize the mechanism of positive-feedback regeneration in a p-n-p-n structure during CMOS latchup transition is developed. It is based on the derived time-varying transient poles in large-signal base-emitter voltages of the lumped equivalent circuit of a p-n-p-n structure. Through calculating the time-varying transient poles during CMOS latchup transition, if is found that there exists a transient pole to change from negative to positive and then this pole changes to negative again. A p-n-p-n structure, which has a stronger positive-feedback regeneration during turn-on transition, will lead to a larger positive transient pole. The time when the positive transient pole occurs during CMOS latchup transition is the time when the positive-feedback regeneration starts. By this positive transient pole, the positive-feedback regenerative process of CMOS latchup can be quantitatively characterized     

Switching conditions for CMOS latch-up path with shunt resistances

Analytical expressions for the switching points of a one-dimensional p-n-p-n representation for a CMOS latch-up path are obtained without the traditional simplifying assumptions. A new criterion for the holding current is established. The results are applicable to the general case where the emitting junctions are shunted by resistances, as well as the simple p-n-p-n structure. The "holding current" of the path is discussed in some detail and predicted values are compared to those obtained experimentally.     

Transient analysis of p-n-p-n optoelectronic devices

p-n-p-n optoelectronic devices were analyzed using a coupled junction model, an equivalent circuit model, and a physical model. The accuracy of these models was confirmed by comparison with experimental data. The result of the authors' analysis was a new understanding of the dynamic properties of p-n-p-n devices. The authors found that the onset of switching depends only on the voltage across the forward-biased outer junctions, not on the total applied bias. Turn-on delay is dependent on the rate of voltage change across the outer junctions and the efficiency of the laser emitter. Fast turn-off of two-terminal devices is theoretically possible by applying a reverse bias during the turn-off transient. dV/dt induced switching can be avoided by proper design. Based on the authors' models, the maximum large-signal operating frequency of two-terminal p-n-p-n devices was estimated to be ~240 MHz     

Layout and bias considerations for preventing transiently triggered latchup in CMOS

This paper investigates several techniques for hardening CMOS curcuitry against transiently triggered latchup. Measurements of critical rise time are made on four variations of the p-n-p-n structure inherent to CMOS. For each structure the n-well and substrate shunt resistances are varied as is the substrate bias. These measurements are performed on both bulk and epi-samples using both topside and backside substrate contacts. Comparison of the parasitic bipolar transistors comprising the p-n-p-n structures reveals that differences in bipolar behavior do not completely explain the differences in p-n-p-n latchup behavior. Test results are used to rate the various hardening techniques.     

Latchup model for the parasitic p-n-p-n path in bulk CMOS

The inherent parasitic bipolar transistors and p-n-p-n paths in monolithic CMOS circuits can be undesirably triggered into the low resistance and high current state, i.e., latchup. To ensure the safe operation for the future scaled CMOS circuits, an accurate latchup model is required for design optimization. A modified lumped resistance model has been developed which is shown to accurately predict the latchup characteristics provided the device parameters are accurately measured and reflect those at the latchup state. The model includes the spreading resistance effect in the substrate by a resistor network and it is shown to be critical in the latch-up characterization. Experimental data that supports this model is presented. The reversed layouts in CMOS circuits have been shown to greatly improve the latchup holding current. The dynamic characterization of latchup, caused by voltage overshoot at the input terminals, has also been characterized. It is shown that a minimum turn-on time for the latchup triggering exists and is governed by the base transit time in the lateral transistor with an enhanced diffusion coefficient from the high injection effect.     

Current balancing in TIL GTO thyristors

Based on the advanced three-transistor model of the two interdigitation levels (TIL) GTO thyristor structure, the theory underlying the device behavior in the ON-state is developed and experimentally validated. The mechanisms underlying the current balancing between the two p-n-p-n sections (standard and quasi-nonregenerative) constituting the TIL GTO structure are disclosed. It is shown that thanks to the current balancing, the effective cathode emitter area increases with the anode current level and that the current density along the standard p-n-p-n sections lags behind the level of load current iT. The broad implications of reported theoretical/experimental results for the physics of the novel device are outlined in the communication. It is shown, e.g., that current balancing is responsible for the drastic boost of the peak interruptable anode current IATOreported for the recently developed TIL GTO thyristors.     

A better understanding of CMOS latch-up

Both lumped-element two-transistor circuit model and two-dimensional finite-element analyses are used to study the latch-up phenomena in CMOS structures. The equivalent circuit model offers a simple view on latch-up, while 2-D modeling provides more physics and quantitative understanding of latch-up. A generalized criterion for p-n-p-n latch-up is derived based on the equivalent circuit. 2-D modeling confirms the latch-up triggering condition described by the criterion. Furthermore, 2-D simulation models the entire latch-up process, including the dynamic triggering stage, and determines the intrinsic steady-state I - V characteristics of p-n-p-n devices.     

A transient analysis of latchup in bulk CMOS

This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure. Not only does the model describe the conditions for transient latchup, but it also predicts a previously unreported phenomenon of dynamic recovery, which we have verified experimentally. Compact Stability criteria are presented for the p-n-p-n structure that delineate the roles of ramp rate and circuit parameters.     

Evaluation of turn-on performance of P-i-N rectifiers and IGBT'sunder zero voltage switching

This paper compares the turn-on performance of two vertical power bipolar devices, viz, P-I-N diode and IGBT, under Zero Voltage Switching (ZVS). Although both the devices are “conductivity modulated” during turn-on, the IGBT carrier dynamics distinctly differ from that of a P-i-N rectifier. It is shown that, for identical drift region parameters, the conductivity modulation in the IGBT is significantly lower compared to that in a P-i-N rectifier mainly because of carrier flow constraints in the IGBT and the inherent bipolar transistor-like carrier distribution in the IGBT. 2-D mixed device and circuit simulations were performed to understand the behavior of the two devices during turn-on under ZVS. The mixed device and circuit simulator was also used to study the effects of variations in the rate of change of current (di/dt) through the device during turn-on, carrier lifetime and temperature on the turn-on behavior of the two bipolar devices under ZVS     

The potential and carrier distributions of a p-n-p-n device in the ON state

The potential and carrier distributions of a p-n-p-n device in the ON state are measured by electrical and optical probing techniques. The measurements are compared with numerical calculations of the potential and carrier distributions and the current-voltage characteristics as a function of device temperature. The calculations are based upon an analysis of the p-n-p-n device at high current densities using an abrupt junction model and including the effects of carrier-carrier scattering, conductivity modulation, and the dependence of emitter efficiency upon current density. The conditions under which the p-n-p-n device may be approximated by a p-n-n⁺device are also considered. The range of applicability of the results includes all ON currents of practical interest in a p-n-p-n device.     

Application of a charge-control model to high-voltage power transistors

Basic charge-control concepts are applied to the problem of predicting the static and large-signal switching characteristics of high-voltage transistors, with particular emphasis placed on the quasi-saturation region. Under the assumptions of unity base transport factor and one-dimensional current flow, simple equations for device electrical characteristics are derived in terms of readily determined device parameters. A two-region model is developed for predicting the turn-on process. Measured turn-on waveforms and collector characteristics are compared with the calculated behavior for a BVCE0= 400 V switching transistor. A comparison with hFE(Ic) data is also given for different temperatures. In all cases, good agreement with the predictions of the model is obtained. Implications of the model with respect to device design and characterization are discussed.     

Infrared microscopy study of anomalous latchup characteristics dueto current redistribution in different parasitic paths

Anomalous effects such as abrupt variations of the latchup current in steady-state conditions and window effects, i.e. the existence of a well-defined interval of I/O injected currents for latchup to occur, can occur during pulsed latchup tests. Infrared microscopy allows the correlation of electrical characteristics with latchup current distribution and reveals that anomalous effects are due to the dynamic competition between different latchup paths. This is confirmed by a SPICE simulation of the lumped equivalent circuit of a CMOS output comprising two coupled p-n-p-n parasitic structures     

Mobility simulation of a novel Si/SiGe FET structure

The theoretical study of a novel Si/SiGe structure combining the advantages of buried channel MOS devices and conventional SiGe FET's is presented. A self-consistent one-dimensional Schrodinger-Poisson simulator has been developed to evaluate the gate dependence of electron effective mobility in the zero-field limit. Room temperature peak mobility values greater than 2800 cm²/Vs are predicted. The proposed structure shows also good turn-on characteristic and linear transconductance behavior, which represents a significant feature in view of possible technology applications     

Turn-on phenomena in optically and electrically fired thyristors

An analytical solution of the time-dependent transport equation including surface recombination and optical injection for a diffused thyristor base is presented. By means of the classical two-transistor model, the turn-on transient may be predicted. Apart from the influence of technological parameters like base width, doping profile, and diffusion length, the effect of optical versus electrical injection as well as surface recombination are discussed. Surface recombination may significantly influence the optical turn-on threshold. Despite the rigorous simplicity of the model, the dynamic turn-on behavior of an optically fired high-voltage thyristor is in very good agreement with the experiment. The data, being presented for a wide range of parameters, are useful for practical design.     

Turn-on jitter of zero-biased nearly single-mode VCSEL's

The turn-on jitter of zero-biased nearly single-mode vertical-cavity surface-emitting lasers (VCSEL's) is experimentally investigated. Since during the turn-on event both the dominant and the suppressed polarization are exited, an analytical expression describing the probability density function of the turn-on delay for a single-mode VCSEL is derived, which accounts for both polarizations. The measurement results and the theory are in good agreement as long as the VCSEL is transversal single-mode     

Voltage shifts in the forward V-I characteristics of p-n-p-n power switches

The forward V-I characteristics of p-n-p-n power switches usually consist of one or more voltage shifts having negative resistance characteristics at small forward current. This phenomenon is attributed to local turning on of the switch due to shorted emitter and/or shorting dots used to enhance the dv/dt capability of the device, since lateral current flow plays a significant role in determining the V-I characteristics at small current, It is shown that the threshold current responsible for the voltage shift phenomenon has an empirical temperature dependence of the formI_{T} sim exp [- a(T - T_{0})]over the temperature range 20-125°C. The hysteresis loop associated with each negative resistance region can be explained in terms of the difference in turn-on current and holding current of a localized area in the vicinity of shorted emitter or shorting dots.     

Transmission line modeling of substrate resistances and CMOS latchup

Substrate resistance in epitaxial-CMOS is more appropriately viewed as a lossy transmission line than as a lumped resistor or as a resistance ladder network. Lossy transmission lines can be used to model a variety of substrate resistance configurations, including the resistance necessary to quantitatively predict turn on of the lateral parasitic bipolar during latchup. Voltage and current distributions predicted by the transmission line model are in excellent agreement with two-dimensional numerical simulations. Parameter values for the model are easily related to vertical doping profiles and to a wide variety of parasitic p-n-p-n layouts. For CMOS design the lateral bipolar's bypass resistor, commonly found in lumped element models of the parasitic p-n-p-n, is replaced by a transfer resistance derived from the transmission line model. Butted substrate contacts are shown to provide a worst-case design situation.     

A new criterion for transient latchup analysis in bulk CMOS

A criterion for transient latchup of p-n-p-n structures initiated by current pulses is described. Based on the circuit-orient model, the terminal currents and voltages of the transistors as a function of the pulsed triggering currents are characterized, and the charge storage within p-n-p-n structures is investigated. It is found that, to maintain the regeneration process, the change of charge stored in junction depletion capacitances of a p-n-p-n structure must be greater than a certain value independent of the triggering currents. Thus, the criterion is constructed in terms of the constant charge storage within a p-n-p-n structure. Applying the criterion, latchup immunity against pulsed triggering currents can be evaluated with respect to process and device parameters. Both SPICE simulations and experimental results confirm the validity of the proposed transient criterion. It is found that the large transit time of bipolar transistors and large well-substrate junction depletion capacitance lead to higher latchup immunity against pulsed triggering currents