Flexible circuit and sensor arrays fabricated by monolithic silicon technology

A novel monolithic batch fabrication method produces arrays of silicon islands containing conventional integrated-circuit components and supported by a flexible polyimide substrate. Islands are interconnected by photolithographically defined gold leads embedded in the polyimide. Because no bonding pads are necessary at island boundaries, lead density between islands is at least twice that available using hybrid techniques. The technology has been used to fabricate thermohaeter arrays for temperature profile measurement during hypertherminal treatment of cancer. An array consists of 20 silicon islands; each island contains one p-n diode, which is used as a thermometer. These linear arrays are 1 mm wide by 0.4 mm thick, with 20-µm-wide by 1-µm-thick gold interconnects on 40-µm centers. The flexible array technology is currently being modified to fabricate two-dimensional arrays of micromechanical sensors for robotic and biomedical uses.     

Reliability of adhesive joined thinned chips on flexible substrates under humid conditions

Thin chips are an interesting option for reducing the thickness of an electronics package. In addition to the reduced size, thinned chips are flexible and can dissipate more heat than thicker ones. Joining of the thin chips can be done using several different techniques. Of these, anisotropic conductive adhesives (ACA) are an interesting option as they have several advantages, such as low bonding temperature and capability for high density interconnections. The reliability of ACA flip chip joints under thermal cycling conditions has been found to increase when thinned chips are used. However, the effect of humidity has not been fully explored. In this study the reliability of thinned chips (50 μm) under humid conditions was investigated using thin flexible substrates. Seven test lots were assembled with thinned chips using two different ACA films and liquid crystal polymer (LCP), polyimide (PI) and thin FR-4 substrates. A high humidity and high temperature test was used to study the reliability of the interconnections. A finite element model (FEM) was used to analyse the stresses in the test samples during testing. Several failures occurred during the test and significant differences between the substrates were seen. Additionally, bonding pressure was found to be a critical factor for the reliability under the humid conditions.     

Multichip modules: next-generation packages

Multichip modules (MCMs), which interconnect multiple bare dice by means of a stack of conductive and dielectric thin films, are discussed. Among their advantages are reduced delays between chips, simplified power distribution, and enhanced dissipation capabilities. Key design demands that should be weighed by IC design engineers planning to use MCMs are examined. They concern transmission delays, power distribution, heat dissipation, and temperature, as well as testing, burn-in, and rework. The various approaches to MCM packages are described. Factory-programmable versus user-programmable options are considered. Techniques for connecting chips to substrates are discussed     

Metal–Polymer Composite Interconnections for Ultra Fine-Pitch Wafer Level Packaging

The decrease in feature sizes of microelectronic devices has underlined the need for higher number of input-outputs (I/Os) in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 mum). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This paper presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress composite structures for extremely fine-pitch wafer level packages. Analytical models for these structures justify the stress reduction at the interfaces and superior reliability as integrated circuit (IC)-package interconnects. Low coefficient of thermal expansion (CTE) polyimide structures with ultra-low stress, high toughness, and strength were fabricated using plasma etching. The dry etching process was tuned to yield a wall angle above 80deg. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. This work also describes a selective electroless plating synthesis route to develop thin IC-package bonding interfaces with lead-free solder. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45degC. The lead-free solder composition was controlled by altering the plating bath formulation. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate using a standard reflow process. Metal-coated polymer structures in conjunction with the thin solder bonding films can provide low-cost high-performance solutions for wafer-level packaging.     

Enhanced outcoupling in flexible organic light-emitting diodes on scattering polyimide substrates

We demonstrate an upscalable approach to increase outcoupling in organic light-emitting diodes (OLEDs) fabricated on flexible substrates. The outcoupling enhancement is enabled by introducing a thin film of microporous polyimide on the backside of silver nanowire (AgNW) electrodes embedded in neat colorless polyimide. This porous polyimide film, prepared by immersion precipitation, utilizes a large index contrast between the polyimide host and randomly distributed air voids, resulting in broadband haze (>75%). In addition, the composite polyimide/AgNW scattering substrate inherits the high thermal (>360 °C), chemical, and mechanical stability of polyimides. The outcoupling efficiency of the composite scattering substrate is studied via optical characterization of the composite substrate and electron microscopy of the scattering film. The flexible scattering substrates compared to glass/indium tin oxide (ITO) allows for a 74% enhancement in external quantum efficiency (EQE) for a phosphorescent green OLED, and 68% EQE enhancement for a phosphorescent white OLED. The outcoupling enhancement remains unharmed after 5000 bending cycles at a 2 mm bending radius. Moreover, the color uniformity over viewing angles is improved, an important feature for lighting applications.     

Metal Conductive Surface Patterning on Photoactive Polyimide

Current fabrication methods for metal interconnects and contacts are generally based on conventional photoresist fabrication procedures that require expensive equipment and multiple material/time‐consuming steps. In this work, a photopatternable polyimide is synthesized via the copolymerization of a functional diamine monomer with a 1,4‐dihydropyridine side‐chain which can decompose under UV irradiation into a pyridine group—a promising ligand for palladium ions. After the absorption of palladium ions, the electroless copper plating is carried out to form metal patterns of copper. Copper patterns with smooth boundaries are confirmed by scanning electron microscope and atomic force microscope. Robust interfacial bonding between the copper and the polyimide film is evidenced by Scotch tape adhesion tests. The photopatternable polyimide has the advantages of low Pd consumption, easy operation without expansive equipment. The linear thermal expansion coefficient of the photopatternable polyimide remains close to the one of copper wire, demonstrating the adaptability of the photopatternable polyimide for integrated circuit application. This work presents the approach of (i) the synthesis of a novel photopatternable polyimide and (ii) its application for making flexible conductive metal structures and patterned metal interconnects, which can be expected to have tremendous potential in the field of flexible electronics.     

HTS and PCT Reliability of Chips and Flex Substrates Assembled Using a Thermosonic Flip-Chip Bonding Process

This study assesses the high-temperature storage (HTS) test and the pressure-cooker test (PCT) reliability of an assembly of chips and flexible substrates. After the chips were bonded onto the flexible substrates, specimens were utilized to assess the HTS test and PCT reliability. After the PCT and HTS tests, the die-shear test was applied to examine changes in die-shear forces. The microstructure of the test specimens was analyzed to evaluate reliability and to identify possible failure mechanisms. When the duration of the HTS test was increased, the percentage of gold bumps that peeled off from the surface of the copper pads on the chip side increased, and a crack was present at the bonding interface between the gold bumps and chip bond pads. This crack was due to thermal stress generated during the HTS test, and degraded the die-shear force of the assembly of chips and flexible substrates. After the PCT, the crack was present at the interface between deposited layers of copper electrodes after the specimens were subjected to the PCT for various durations. Moisture penetrated into the deposited layers of the copper electrodes, deposited layers lost their adhesion, and the crack progressed from the corner into the central bond area as the test duration increased. To improve the PCT reliability of assemblies of chips and flexible substrates using the thermosonic flip-chip bonding process, one must prevent moisture from penetrating into deposited layers of copper electrodes and prevent crack formation at the interface between nickel and copper layers. Underfill would be an effective approach to prevent moisture from penetrating into deposited layers during the PCT, thereby improving the reliability of the samples during the PCT.     

Thermosonic bonding of gold wire onto silver bonding layer on the bond pads of chips with copper interconnects

A copper pad oxidizes easily at elevated temperatures during thermosonic wire bonding for chips with copper interconnects. The bondability and bonding strength of a gold wire onto a bare copper pad are seriously degraded by the formation of a copper oxide film. A new bonding approach is proposed to overcome this intrinsic drawback of the copper pad. A silver layer is deposited as a bonding layer on the surface of copper pads. Both the ball-shear force and the wire-pull force of a gold wire bonded onto copper pads with silver bonding layers far exceed the minimum values stated in the JEDEC standard and MIL specifications. The silver bonding layer improves bonding between the gold ball and copper pads. The reliability of gold ball bonds on a bond pad is verified in a high-temperature storage (HTS) test. The bonding strength increases with the storage time and far exceeds that required by the relevant industrial codes. The superior bondability and high strength after the HTS test were interpreted with reference to the results of electron probe x-ray microanalyzer (EPMA) analysis. This use of a silver bonding layer may make the fabrication of copper chips simpler than by other protective schemes.     

Effects of bonding parameters on the reliability performance of anisotropic conductive adhesive interconnects for flip-chip-on-flex packages assembly II. Different bonding pressure

The effects of different bonding temperatures during flip-chip-on-flex (FCOF) assembly in relation to the performance of anisotropic conductive adhesive (ACF) interconnect were investigated. Two types of flip chips were used in this study. It was found that Ni bumps formed better interconnections than bumpless FCOF packages. Aluminium oxide was observed and was thought to be the main cause of the increased in contact resistance after the moisture-soak tests. The conductive particles were not fully compressed by the bumps and pads and gaps were observed between the conductive particles and Cu pads in bumpless packages. Conductive particles in the Ni bump FCOF packages were tightly trapped between the bumps and pads and hence gave better connections. The performance of the ACF interconnects were affected by the degree of curing of the ACF, which was determined by the bonding temperature.     

Evaluation of wire bonding performance, process conditions, and metallurgical integrity of chip on board wire bonds

Chip on board wire bonding presents challenges to modern wire bonding technology which include smaller, closely spaced wire bond pads; bonding to soft substrates without special processing and pad construction; and diverse first bond and second bond metallurgies. These challenges are addressed by extensive bonding accuracy tests, a design of experiments approach for optimizing wire bond process parameters, reliability testing, and detailed materials characterization of the metallurgical integrity of the wire bonds. The thermo-mechanical integrity of the wire bond interconnects was evaluated by wire pull and hot storage tests. Hot storage testing allowed for detection of samples with an electrolytic gold surface finish that was too thin, and exhibited a contamination-corrosion condition of the nickel under-plating. Other samples with an excessively thick, rough textured nickel under-plating layer exhibited poor wire bond-ability. The methodology of materials analyses of the metallurgy of the wire bond interconnects is described. The paper illustrates a wire bond lift technique that is used to inspect for cratering damage and the “area-uniformity” of gold aluminum intermetallics. An improved understanding of the wire bonding process was achieved by showing the dependence of the visual appearance of the wire bonds on wire bond process parameters.     

Effects of bonding parameters on the reliability performance of anisotropic conductive adhesive interconnects for flip-chip-on-flex packages assembly I. Different bonding temperature

The effects of different bonding temperatures during flip-chip-on-flex (FCOF) assembly in relation to the performance of anisotropic conductive adhesive (ACF) interconnect were investigated. Two types of flip chips were used in this study. It was found that Ni bumps formed better interconnections than bumpless FCOF packages. Aluminium oxide was observed and was thought to be the main cause of the increased in contact resistance after the moisture-soak tests. The conductive particles were not fully compressed by the bumps and pads and gaps were observed between the conductive particles and Cu pads in bumpless packages. Conductive particles in the Ni bump FCOF packages were tightly trapped between the bumps and pads and hence gave better connections. The performance of the ACF interconnects were affected by the degree of curing of the ACF, which was determined by the bonding temperature.     

LTCC基板上薄膜多层布线工艺技术

LTCC基板上薄膜多层布线工艺是MCM-C/D多芯片组件的关键技术。它可以充分利用LTCC布线层数多、可实现无源元件埋置于基板内层、薄膜细线条等优点,从而使芯片等元器件能够在基板上更加有效地实现高密度的组装互连。文章介绍了LTCC基板上薄膜多层布线工艺技术,通过对导带形成技术、通孔柱形成技术和聚酰亚胺介质膜技术的研究,解决了在LTCC基板上薄膜多层布线中介质膜"龟裂",通孔接触电阻大、断路,对导带的保护以及电镀前的基片处理等工艺难题。     

Smart tooling for assembly of thin flexible systems

Emerging electronic assemblies are demanding lower cost, lighter weight, miniaturized packages mounted on thin flexible circuit boards and/or flex circuits. However, the compliant nature of the flex substrates poses new processing technology challenges for standard surface mount assembly equipment. A particular challenge is fixture tooling. The flexible substrate experiences significant transverse displacements under perpendicular assembly and/or fixturing forces during solder paste printing and component placement processes. The transverse displacements result in misregistration of the component leads and substrate bond pads, leading to severe assembly process defects. The solder reflow process further complicates the issue due to the thermo-mechanical warpage induced. Conventional assembly equipment utilizes dedicated tooling designed to handle rigid circuit board assemblies. As electronic assemblies move toward very fine pitch surface mount packages, chip scale packages, and flip chip attachment assembled to thin flexible double-sided circuit boards, reengineered and specialized dedicated tooling for fixturing flexible substrates in standard assembly equipment are becoming extremely important. This paper focuses on developing analysis methodologies and theories for implementing machine dedicated Smart Tooling. The primary goals being to determine the impact of fixturing on assembly process quality and to determine optimum fixturing configurations for thin flexible circuit board assemblies based on circuit design data. A mathematical model to describe both transverse and perpendicular displacements of flex substrates is developed, and its closed form solution for transverse displacements is obtained. Fixturing configurations based on a perimeter support technique of flex substrates is analyzed to minimize transverse displacements     

Closed-form expressions for the series impedance parameters of on-chip interconnects on multilayer silicon substrates

This paper presents accurate closed-form expressions for the frequency-dependent series impedance parameters of on-chip interconnects over general multilayer conductive silicon substrates. The closed-form expressions are obtained from a generalized complex image approach combined with a surface impedance formulation that takes into account the effects of the distributed eddy currents in the multilayer conductive substrate. Results for single and coupled microstrips on multilayer conductive substrates are shown over a broadband frequency range of 20 GHz and compared with full-wave electromagnetic solutions. It is demonstrated that a thin, heavily-doped channel-stop layer may contribute significantly to the series resistance at higher frequencies. The new approach is further validated for a coplanar waveguide interconnect by comparison with measurement data.     

Prototyping of a reliable 3D flexible IC cube package by laser micromachining

A newly designed three-dimensional (3D) flexible circuit as a package with five IC chips has been invented, and the prototype of the 3D package using laser micromachining has been successfully demonstrated. Fabrication processes of the 3D package consist of (1) preparation of printed wiring on the flexible substrate, (2) selective polyimide material removing on contact pads using UV laser (3) component placing and soldering, and (4) preparation of bending windows by laser micromachining. The production of the so-called bending window is a unique application of laser material processing. These windows can be used in flexible circuits to define the exact position of deformation. It is done by reducing the thickness of the flexible substrate in a well-defined, narrow line. The unique feature of this newly developed package is the 2D design for a 3D structure. According to this design, 55% area reduction can be obtained without any designing and overheating problems, which usually occurs. Furthermore, the new 3D package design can simplify processes such as I/O redistribution, chip cooling, and package formation. It is proven that the mechanical integrity of the prototype 3D stacked package meets the requirements of the 85 °C/85% test.     

Reliability of Conductive Adhesives as a Pb-free Alternative in Flip-Chip Applications

The temperature-humidity reliability of anisotropic conductive film (ACF) and non-conductive film (NCF) interconnects is investigated by measuring the interconnect resistance during temperature-humidity testing (THT) at 85°C and 85% relative humidity. The four-point probe method was used to measure the interconnect resistance of the adhesive joints constructed with Au bumps on Si chips and Cu pads on flexible printed circuits (FPCs). The interconnect resistance of the ACF joints was markedly higher than that of the NCF joints, mainly due to the constriction of the current flow and the intrinsic resistance of the conductive particles in the ACF joints. The interconnect resistances of both interconnects decreased with increasing bonding force, and subsequently converged to about 10 mΩ and 1 mΩ at a bonding force of 70 N and 80 N, for the ACF and NCF joints, respectively. During the THT, two different conduction behaviors were observed: increased interconnect resistance and the termination of Ohmic behavior. The former was due to the decreased contact area caused by z-directional swelling of the adhesives, whereas the latter was caused by either contact opening in the adhesive joints or interface cracking.     

A Transparent,Smooth, Thermally Robust,Conductive Polyimide for Flexible Electronics

In this work, a thermally and mechanically robust, smooth transparent conductor composed of silver nanowires embedded in a colorless polyimide substrate is introduced. The polyimide is exceptionally chemically, mechanically, and thermally stable. While silver nanowire networks tend not to be thermally stable to high temperatures, the addition of a titania coating on the nano­wires dramatically increases their thermal stability. This allows for the polyimide to be thermally imidized at 360 °C with the silver nanowires in place, creating a smooth (<1 nm root mean square roughness), conductive surface. These transparent conducting substrate‐cum‐electrodes exhibit a conductivity ratio figure of merit of 272, significantly outperforming commercially available indium‐tin‐oxide (ITO)‐coated plastics. The conductive polymide is subjected to various mechanical tests and is used as a substrate for a thermally deposited, flexible, organic light‐emitting diode, which shows improved device performance compared to a control device made on ITO coated glass.     

Effect of PVP-coated silver nanoparticles using laser direct patterning process by photothermal effect

Laser direct patterning of silver nanoparticles (AgNPs) conductive patterns on a polyimide substrate using photothermal effect of nanoparticles provides various advantages for applications in flexible electronics. Two PVP content AgNPs were used in this research. Since the thin and thick PVP-coated AgNPs have a strong optical absorption at 426 and 405 nm, respectively, a UV laser (405 nm and 60 mW) is used to trigger AgNPs to convert light into heat due to photothermal effect of nanoparticles. After UV laser beam irradiating on the AgNPs thin film, the AgNPs aggregate into larger conducting grains and improve the adhesion between AgNPs and the polyimide substrate at the same time. Then the desired AgNPs conductive lines (line width: 30 μm, line space: 70 μm) are formed after washing the unirradiated AgNPs. By this method, we have demonstrated a 5 μm width AgNPs conductive line. In the mean time, we also found out that the higher PVP content, the laser direct patterning of AgNPs conductive lines would have more straight and smooth boundaries. And the adhesion between the AgNPs conductive patterns and PI substrate would be better while using higher PVP content AgNPs.     

Buried active and passive components

The coming generations of portable products require significant improvement of packaging technologies, mainly due to increasing signal frequencies and the demand for higher density of functions. State of the art are organic substrates with high-density build-up layers and micro-vias, equipped on both sides with discrete passive and active components. The space requirement of active chips can be already reduced to a minimum by implementing CSPs (chip size packages) or flip chips. A further miniaturization however requires a 3-dimensional integration of components. Besides miniaturization the new applications require signal frequencies of several GHz. In order to maintain signal integrity, much shorter and impedance-matched interconnects between chips and other components are required. Here a new approach will be described which allows extreme dense 3-dimensional integration and very short interconnects combined with the generation of integrated resistors. This approach, called ?Chip in Polymer“ is based on the integration of extremely thin components into build-up layers of printed circuit boards.     

挠性基板制造工艺

应用于IC封装(Integrated Circuit,集成电路)的FPC(Flexible Printing Circuit,挠性印制板)称为挠性基板。随着电子产品向高密度、小型化、高可靠性方向发展,挠性基板线路制造工艺也从传统的减成法发展到半加成法,同时,一些新型的薄型挠性基板及埋嵌器件挠性基板也逐渐应用于航天、医疗及消费类电子等领域[1]。