Influence of crystallinity of as-deposited Ge film on formation of quantum dot in carbon-mediated solid-phase epitaxy

The influence of crystallinity of as-deposited Ge films on Ge quantum dot (QD) formation via carbon (C)-mediated solid-phase epitaxy (SPE) was investigated. The samples were fabricated by solid-source molecular beam epitaxy (MBE). Ge/C/Si structure was formed by sequential deposition of C and Ge at deposition temperature (T_D) of 150–400 °C, and it was heat-treated in the MBE chamber at 650 °C. In the case of amorphous or a mixture of amorphous and nano-crystalline Ge film grown for T_D ≤250 °C, density of QDs increased with increasing T_D due to the increase of C-Ge bonds in Ge layer. Ge QDs with diameter of 9.2±2.1 nm were formed in the highest density of 8.3×10¹¹ cm⁻² for T_D =250 °C. On the contrary, in the case of polycrystalline Ge film for T_D ≥300 °C, density of QDs decreased slightly. This is because C incorporation into Ge layer during SPE was suppressed due to the as-crystallized columnar grains. These results suggest that as-deposited Ge film in a mixture of amorphous and nano-crystalline state is suitable to form small and dense Ge QDs via C-mediated SPE.     

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Low-temperature formation of self-assembled Ge quantum dots on Si(100) under high carbon mediation via solid-phase epitaxy

CMOS-compatible low-temperature formation of self-assembled Ge quantum dots (QDs) by carbon (C) mediation via a solid-phase epitaxy (SPE) has been demonstrated. The samples were prepared by a solid-source molecular beam epitaxy (MBE) system. C and Ge were successively deposited on Si(100) at 200 °C and Ge/C/Si heterostructure was annealed in the MBE chamber. Sparse Volmer-Weber mode Ge dots without a wetting layer were formed for C coverage (θ_C) of 0.25 and 0.5 ML by lowering SPE temperature (T_S) to 450 °C, but small and dense Stranski-Krastanov (SK)-mode Ge QDs with the wetting layer were obtained with increasing C coverage of 0.75 ML even at 450 °C. From the investigation of SPE temperature effect on Ge QD formation for θ_C of 0.75 ML, SK-mode Ge QDs of about 10 nm in diameter and of about 4.5×10¹¹ cm⁻² in density were formed at T_S≥400 °C. The wetting layer of SK-mode QDs was almost constant 0.2-nm thick at T_S≥450 °C. Measurements of chemical binding states of C in Ge QDs and at Ge/Si interface revealed that a large amount of C–Ge bonds were formed in the wetting layer for high C coverage, and the formation of C–Ge bonds, together with the formation of C–Si bonds, enabled the low-temperature formation of small and dense Ge QDs. These results suggest that the C-mediated solid-phase epitaxy is effective to form small and dense SK-mode QDs at low temperature.     

Photoluminescence of phosphorous doped Ge on Si (100)

Photoluminescence (PL) of selectively grown phosphorus (P) doped germanium (Ge) is investigated. 350–600 nm thick P-doped Ge is grown on 100 nm thick P-doped Ge buffer layer, which is annealed at 800 °C before the main part of Ge deposition. In the case of Ge deposited at 325 °C, approximately two times higher PL intensity is observed by P doping of ~3.2×10¹⁹ cm⁻³. Further increase of PL intensity by a factor of 1.5 is observed by increasing the growth temperature from 325 °C to 400 °C due to improved crystal quality. Varying PH₃ partial pressure at 400 °C, red shift of the PL occurred with increasing P concentration due to higher bandgap narrowing. With increasing P concentration up to ~1.4×10¹⁹ cm⁻³ at 400 °C the PL peak intensity increases by filling electrons into the L valley and decreases due to enhanced point defect concentration and degraded crystallinity. By post-annealing at 500–800 °C, the PL intensity is further increased by a factor of 2.5 because of increased active P concentration and improved crystal quality. Reduced direct bandgap energy by introducing tensile strain is also observed.     

Planar copper-tin inter-metallic film formation on strained substrates

This paper presents the results of four-point bending tests investigating the effects of substrate strain on the growth ɛ of interfacial Cu–Sn inter-metallic compounds (IMCs). Test specimens were cut into strips, 27.5 mm in length and 5 mm in width, from 4 in. double polished silicon wafers. A very thin adhesion layer (Ta) was deposited on the silicon substrate by sputtering followed by a 10 μm thick layer of copper using electroplating. Finally, a 30 μm tin layer was deposited over the copper film also by electroplating. Samples were then placed in a furnace at 200 °C to undergo bending in order to introduce in-plane strain under tension or compression. Control samples also underwent the same treatment without applied strain. Our aim was to investigate the influence of substrate strain and aging time on the formation of IMCs (1.54 × 10⁻⁴, 2.3 × 10⁻⁴ and 3.46 × 10⁻⁴). The thickness and separation of each phase (Cu₃Sn) and η (Cu₆Sn₅) are clearly visible in scanning electron microscope images. Compressive strain and tensile strain both increased the thickness of the IMC layer during the aging process; however, the effects of compressive strain were more pronounced than those of tensile strain. We hypothesize that the increase in IMC thickness is related to the strain enhanced out-diffusion of Cu towards the solder as well as strain in the underlying lattice at the diffusion interface.     

Ultra-low-energy ion-beam-synthesis of Ge nanocrystals in thin ALD Al2O3 layers for memory applications

Structural and electrical properties of ALD-grown 5 and 7 nm-thick Al₂O₃ layers before and after implantation of Ge ions (1 keV, 0.5–1 × 10¹⁶ cm^?2) and thermal annealing at temperatures in the 700–1050 °C range are reported. Transmission Electron Microscopy reveals the development of a 1 nm-thick SiO₂-rich layer at the Al₂O₃/Si substrate interface as well as the formation of Ge nanocrystals with a mean diameter of ～5 nm inside the implanted Al₂O₃ layers after annealing at 800 °C for 20 min. Electrical measurements performed on metal–insulator–semiconductor capacitors using Ge-implanted and annealed Al₂O₃ layers reveal charge storage at low-electric fields mainly due to location of the Ge nanocrystals at a tunnelling distance from the substrate and their spatial dispersion inside the Al₂O₃ layers.     

Spirobifluorene/sulfone hybrid: Highly efficient solution-processable material for UV–violet electrofluorescence,blue and green phosphorescent OLEDs

A high efficient UV–violet emission type material bis[4-(9,9′-spirobifluorene-2-yl)phenyl] sulfone (SF-DPSO) has been synthesized by incorporating electron deficient sulfone and morphologically stable spirobifluorene into one molecule. The steric and bulky compound SF-DPSO exhibits an excellent solid state photoluminescence quantum yield (Φ_PL = 92%), high glass transition temperature (T_g = 211 °C) and high triplet energy (E_T = 2.85 eV). In addition, the uniform amorphous thin film could be formed by spin-coating from its solution. These promising physical properties of the material made it suitable for using as UV–violet emitter in non-doped device and appropriate host in phosphorescent OLEDs. With SF-DPSO as an emitter, the non-doped solution processed device achieved an efficient UV–violet emission with the EL peak around 400 nm. By using SF-DPSO as a host, solution processed blue and green phosphorescent organic light emitting diodes showed a high luminous efficiency of 13.7 and 30.2 cd A⁻¹, respectively.     

Investigations on phosphorus doped amorphous/nanocrystalline silicon films deposited by a filtered cathodic vacuum arc technique in the presence of hydrogen gas

Phosphorus doped amorphous/nanocrystalline silicon (a-Si:H/nc-Si:H) thin films have been deposited by a filtered cathodic vacuum arc (FCVA) technique in the presence of hydrogen gas at different substrate temperatures (T_s) ranging from room temperature (RT) to 350 °C. The films have been characterized by using X-ray diffraction (XRD), Raman spectroscopy, Fourier transform infrared (FTIR) spectroscopy, dark conductivity (σ_D), activation energy (ΔE), optical band gap (E_g) and secondary ion mass spectroscopy. The XRD patterns show that RT grown film is amorphous in nature but high temperature (225 and 350 °C) deposited films exhibit nanocrystalline structure with (111) and (220) crystal orientations. The crystallite size of higher temperature grown silicon film evaluated was between 13 and 25 nm. Raman spectra reveal the amorphous nature of the film deposited at RT, whereas higher temperature deposited films show crystalline nature. The crystalline volume fraction of the silicon film deposited at higher temperatures (225 and 350 °C) was estimated to be 58 and 72%. With the increase of T_s, the bonding configuration changes from mono-hydride to di-hydride as revealed by the FTIR spectra. The values of σ_D, ΔE and E_g of silicon films deposited at different T_s were found to be in the range of 5.37×10⁻⁴–1.04 Ω⁻¹ cm⁻¹, 0.05–0.45 eV and 1.42–1.83 eV, respectively. Photoconduction of 3.5% has also been observed in n-type nc-Si:H films with the response and recovery times of 9 and 12 s, respectively. A n-type nc-Si:H/p-type c-Si heterojunction diode was fabricated which showed the diode quality factor between 1.6 and 1.8.     

Computational studies on the radiative and nonradiative processes of luminescent N-heteroleptic platinum(II) complexes

Three N-heteroleptic Pt(II) complexes, [Pt(C^C)(O^O)] [O^O = acetylacetonate, C^C = 1-phenyl-1,2,4-triazol-5-ylidene (1), C^C = 4-phenyl-1,2,4-triazol-5-ylidene (2), C^C = 2-phenylpyrazine (3)] have been investigated with density functional theory (DFT) and time-dependent density functional theory (TDDFT). The radiative decay rate constants of complexes 1–3 have been discussed with the oscillator strength (f_n), the strength of spin–orbit coupling (SOC) interaction between the lowest energy triplet excited state (T₁) and singlet excited states (S_n), and the energy gaps between E(T₁) and E(S_n). To illustrate the nonradiative decay processes, the transition states between triplet metal-centered (³MC) and T₁ states have been optimized and were verified with the calculations of vibrational frequencies and intrinsic reaction coordinate (IRC). In addition, the minimum energy crossing points (MECPs) between ³MC and ground states (S₀) were optimized. At last, the potential energy curves relevant to the nonradiative decay pathways are simulated. The results show that complex 3 has the biggest photoluminescence quantum yield because the complex 3 has the biggest radiative decay rate constant and the smallest nonradiative decay rate constant in complexes 1–3.     

Paramagnetic Ge dangling bond type defects at (1 0 0)Si1−xGex/SiO2 interfaces (Invited Paper)

The work addresses the occurrence of Ge dangling bond type point defects at Ge_xSi_1?x/insulator interfaces as evidenced by conventional electron spin resonance (ESR) spectroscopy. Using multifrequency ESR, we report on the observation and characterization of a first nontrigonal Ge dangling bond (DB)-type interface defect in SiO₂/(1 0 0)Ge_xSi_1?x/SiO₂/(1 0 0)Si heterostructures (0.27 ? x ? 0.93) manufactured by the condensation technique, a selective oxidation method enabling Ge enrichment of a buried epitaxial Si-rich SiGe layer. The center, exhibiting monoclinic-I (C_2v) symmetry is observed in highest densities of ～7 × 10¹² cm^?2 of Ge_xSi_1?x/SiO₂ interface for x ～ 0.7, to disappear for x outside the ]0.45–0.87[ interval, with remarkably no copresence of Si P_b-type centers. Neither are trigonal Ge DB centers observed, enabling unequivocal spectral analysis. Initial study of the defect passivation under annealing in molecular H₂ has been carried out. On the basis of all data the defect is depicted as a Ge P_b1-type center, i.e., distinct from a trigonal basic Ge P_b(0)-type center (Ge₃Ge). The modalities of the defect’s occurrence as unique interface mismatch healing defect is discussed, which may widen our understanding of interfacial DB centers in general.     

Performance analysis of nanoscale GeSn MOSFETs for mixed-mode circuit applications

Using extensive numerical analysis we investigate the impact of Sn ranging 0–6% in compressively strained GeSn on insulator (GeSnOI) MOSFETs for mixed-mode circuit performance at channel lengths (L_g) ranging 100–20 nm with channel thickness values of 10 and 5 nm. Our results reveal that 10 nm thick Ge_0.94Sn_0.06 channel MOSFETs produce improvement of peak transconductance g_m, peak gain Av, peak cut-off frequency f_T and maximum frequency of oscillations f_max by 80.5%, 18.8%, 83.5% and 81.7%, respectively compared with equivalent GeOI device at L_g =20 nm. Furthermore, such devices exhibit 78.8% increase in ON-current I_ON while yield 44.5% reduction in delay as compared to Ge control devices enabling them attractive for logic applications. Thinning of the channel thickness from 10 to 5 nm increases peak Av, peak transconductance efficiency and reduces output conductance and OFF-current I_OFF while degrading other parameters in all GeSnOI and control Ge devices.     

Interface studies of ALD-grown metal oxide insulators on Ge and III–V semiconductors (Invited Paper)

Atomic layer deposited (ALD) HfO₂/GeO_xN_y/Ge(1 0 0) and Al₂O₃/In_0.53Ga_0.47As(1 0 0) ? 4 × 2 gate stacks were analyzed both by MOS capacitor electrical characterization and by advanced physical characterization to correlate the presence of electrically-active defects with chemical bonding across the insulator/channel interface. By controlled in situ plasma nitridation of Ge and post-ALD annealing, the capacitance-derived equivalent oxide thickness was reduced to 1.3 nm for 5 nm HfO₂ layers, and mid-gap density of interface states, D_it = 3 × 10¹¹ cm^?2 eV^?1, was obtained. In contrast to the Ge case, where an engineered interface layer greatly improves electrical characteristics, we show that ALD-Al₂O₃ deposited on the In_0.53Ga_0.47As (1 0 0) ? 4 × 2 surface after in situ thermal desorption in the ALD chamber of a protective As cap results in an atomically-abrupt and unpinned interface. By avoiding subcutaneous oxidation of the InGaAs channel during Al₂O₃ deposition, a relatively passive gate oxide/III–V interface is formed.     

Depression of the superconducting critical temperature and finite-size scaling relation in YBa2Cu3O7−δ/La2/3Ca1/3MnO3 bilayers

High-quality YBa₂Cu₃O_7?δ/La_2/3Ca_1/3MnO₃ (YBCO/LCMO) bilayers were fabricated on (0 0 1)-oriented SrTiO₃ (STO) substrates by dc-sputtering technique. Bottom layer was always LCMO since it grows better on STO than on YBCO. The thickness of the ferromagnetic layer varied between 5 and 35 monolayers (～2–13 nm) and that of the top YBCO was fixed at 10 monolayers (～12 nm). The transport properties of the YBCO layers as well as the magnetic properties of the LCMO counterparts were studied as a function of the LCMO layer thickness. A sizeable depression of the Curie temperature (T_C) of the LCMO layers from the bulk to lower temperatures is observed when decreasing their layer thickness d_LCMO, which might be ascribed to intrinsic dimensionality effects or strain-induced phenomena. On the contrary, the superconducting critical temperature of the YBCO layer T_S displays a sudden strong decrease at a critical LCMO thickness of ～12 nm. Since no dramatic change of the structural and morphological quality of the YBCO top layers with increasing d_LCMO is observed, the suppression of T_S of the YBCO layers should take place via proximity effect due to the increasing magnetization strength in the LCMO layer. However, extrinsic factors like interface strain, interdiffusion of cations between YBCO and LCMO or injection of spin-polarized carriers from the magnetic into the superconducting layer could also play an important role or even to be directly responsible for the observed depressed T_S.     

Fabrication of the flexible pentacene thin-film transistors on 304 and 430 stainless steel (SS) substrate

Flexible organic thin-film transistors (OTFT) were fabricated on 304 and 430 stainless steel (SS) substrate with aluminum oxide as a gate insulator and pentacene as an organic semiconductor. Chemical mechanical polishing (CMP) process was used to study the effect of the SS roughens on the dielectric properties of the gate insulator and OTFT characteristics. The surface roughness was decreased from 33.8 nm for 304 SS and 19.5 nm for 430 SS down to ～2.5 nm. The leakage current of the metal–insulator–metal (MIM) structure (Au/Al₂O₃/SS) was reduced with polishing. Mobility and on/off ratio of pentacene TFT with bare SS showed a wide range of values between 0.005 and 0.36 cm²/Vs and between 10³ and 10⁵ depending on the location in the substrate. Pentacene TFTs on polished SS showed an improved performance with a mobility of 0.24–0.42 cm²/Vs regardless of the location in the substrate and on/off ratio of ～10⁵. With self assembled monolayer formation of octadecyltrichlorosilane (OTS) on insulator surface, mobility and on/off ratio of pentacene TFT on polished SS was improved up to 0.85cm²/Vs and ～10⁶. I–V characteristics of pentacene TFT with OTS treated Al₂O₃/304 SS was also obtained in the bent state with a bending diameter (D) of 24, 45 or 70 mm and it was confirmed that the device performed well both in the linear regime and the saturation regime.     

The effect of external stress on the electrical characteristics of AlGaN/GaN HEMTs

The electrical characteristics of AlGaN/GaN high electron mobility transistors under the application of uniform in-plane tensile and compressive stress were measured. The results demonstrate the change of the drain–source I_ds–V_ds characteristics as a function of the external stress. The output current at V_ds = 10 V increases linearly with the stress with the slope about 3 × 10⁻⁶ A MPa⁻¹. It is associated with the piezoelectric effect and kink effect. Moreover, the magnitude of the kink effect is found to be affected by the stress. It displays a linear changing trend with the slope of 3.3 × 10⁻⁴ mS MPa⁻¹ within the stress level. The energy band structure is suggested to be responsible for the dependence of the kink effect on the stress.     

Functionalized terfluorene for solution-processed high efficiency blue fluorescence OLED and electrophosphorescent devices

A new multifunctional blue-emitting terfluorene derivative (TFDPA) featured with triphenylamine groups for hole-transportation and long alkyl chains for solution processability on the conjugation inert bridge centers was reported. TFDPA can give homogeneous thin film by solution process and exhibits high hole mobility (μ_h ≈ 10^?3 cm² V^?1 s^?1) and suitable HOMO for hole injection. Particularly, TFDPA performs efficient deep-blue emission with high quantum yield (～100% in solution, 43% in thin film) and suitable triplet energy (E_T = 2.28 eV), making solution-processed OLED devices of using TFDPA as blue emitter and as host for iridium-containing phosphorescent dopants feasible. The solution-processed nondoped blue OLED device gives saturated deep-blue electroluminescence [CIE = (0.17, 0.07)] with EQE of 2.7%. TFDPA-hosted electrophosphorescent devices performed with EQE of 6.5% for yellow [(Bt)₂Ir(acac)], 9.3% of orange [Ir(2–phq)₃], and 6.9% of red [(Mpq)₂Ir(acac)], respectively. In addition, with careful control on the doping concentration of [(Bt)₂Ir(acac)], a solution-processed fluorescence–phosphorescence hybrided two-color-based WOLED with EQE of 3.6% and CIE coordinate of (0.38, 0.33) was successfully achieved.     

Growth of a Ge layer on 8 in. Si (100) substrates by rapid thermal chemical vapor deposition

We have made the successful growth of Ge layer on 8 in. Si (100) substrates by rapid thermal chemical vapor deposition (RTCVD). In order to overcome the large lattice mismatch between Ge and Si, we used a two-step growth method. Our method shows the uniformity of the thickness and good quality Ge layer with a homogeneous distribution of tensile strain and a lower etch pit density (EPD) in order of 10⁵ cm⁻². The surface morphology is very smooth and the root mean square (RMS) of the surface roughness was 0.27 nm. The photocurrent spectra were dominated by the Ge layer related transition that corresponding to the transitions of the Si and Ge. The roll-off in photocurrent spectra beyond 1600 nm is expected due to the decreased absorption of Ge.     

Germanium surface and interfaces (Invited Paper)

Germanium surface and interfaces are modeled based on the requirement that surface charge neutrality is satisfied. It is found that Ge interfaces have remarkable electronic properties stemming from the fact that the energy gap is low and the CNL is located very low in the gap close to the valence band. Because of this, acceptor defects (probably dangling bonds) are easily filled building a negative charge at the interface which easily inverts the surface of n-type Ge at no gate bias and for low doping N_D and moderate to high interface state density D_it. This has important consequence in the electrical characteristics of Ge transistors. In p-channel FETs, an undesired positive threshold voltage V_T of +0.2 to +0.5 V is predicted depending on N_D, D_it and the equivalent oxide thickness. In n-channel FETs, inversion is inhibited and V_T could become higher than 1 V if the D_it is well in excess of 10¹³ eV^?1 cm^?2.     

Effect of the film thickness on the crystal structure and ferroelectric properties of (Hf0.5Zr0.5)O2 thin films deposited on various substrates

In this work, the effect of the film thickness on the crystal structure and ferroelectric properties of (Hf_0.5Zr_0.5)O₂ thin films was investigated. The thin films were deposited on (111) Pt-coated SiO₂, Si, and CaF₂ substrates with thermal expansion coefficients of 0.47, 4.5, and 22×10⁻⁶/°C, respectively. From the X-ray diffraction measurements, it was found that the (Hf_0.5Zr_0.5)O₂ thin films deposited on the SiO₂ and CaF₂ substrates experienced in-plane tensile and compressive strains, respectively, in comparison with the films deposited on the Si substrates. For films deposited on all three substrates, the volume fraction of the monoclinic phase increased with increasing film thickness, with the SiO₂ substrate having the lowest monoclinic phase volume fraction at all film thicknesses tested. The grain size of the films, which is an important factor for the formation of the ferroelectric phase, remained almost constant at about 10 nm in diameter regardless of the film thickness and type of substrate utilized. Ferroelectricity was observed for the 17 nm-thick films deposited on SiO₂ and Si substrates, and the maximum remanent polarization (P_r) value of 9.3 µC/cm² was obtained for films deposited on the SiO₂ substrate. In contrast, ferroelectricity with P_r=4.4 µC/cm² was observed only for film on SiO₂ substrate in case of 55 nm-thick films. These results suggest that the films under in-plane tensile strain results in the larger ferroelectricity for 17 nm-thick films and have a ferroelectricity up to 55 nm-thick films.     

Investigation of deep level defects in copper irradiated bipolar junction transistor

Commercial bipolar junction transistor (2N 2219A, npn) irradiated with 150 MeV Cu¹¹⁺-ions with fluence of the order 10¹² ions cm^?2, is studied for radiation induced gain degradation and deep level defects. I–V measurements are made to study the gain degradation as a function of ion fluence. The properties such as activation energy, trap concentration and capture cross-section of deep levels are studied by deep level transient spectroscopy (DLTS). Minority carrier trap levels with energies ranging from E_C ? 0.164 eV to E_C ? 0.695 eV are observed in the base–collector junction of the transistor. Majority carrier trap levels are also observed with energies ranging from E_V + 0.203 eV to E_V + 0.526 eV. The irradiated transistor is subjected to isothermal and isochronal annealing. The defects are seen to anneal above 350 °C. The defects generated in the base region of the transistor by displacement damage appear to be responsible for transistor gain degradation.