The effect of temperature on the growth and properties of green light-emitting In0.5Ga0.5N films prepared by reactive sputtering with single cermet target

We have grown In_0.5Ga_0.5N films on SiO₂/Si (100) substrate at 100–400 °C for 90 min by rf reactive sputtering with single cermet target. The target was made by hot pressing the mixture of metallic indium, gallium and ceramic gallium nitride powder. X-ray diffraction (XRD) measurements indicated that In_0.5Ga_0.5N films had wurtzite structure and showed the preferential (1 0 -1 0) diffraction. Both SEM and AFM showed that In_0.5Ga_0.5N films were smooth and had small roughness of 0.6 nm. Optical properties were measured by photoluminescence (PL) spectra from room temperature to low temperature of 20 K. The 2.28 eV green emission was achieved at room temperature for all our InGaN films. The electrical properties of In_0.5Ga_0.5N films on a SiO₂/Si (100) substrate were measured by the Hall measurement at room temperature. InGaN films showed the electron concentration of 1.51×10²⁰–1.90×10²⁰ cm⁻³ and mobility of 5.94–10.5 cm² V⁻¹ s⁻¹. Alloying of InN and GaN was confirmed for the sputtered InGaN.     

Self-aligned inversion n-channel In0.2Ga0.8As/GaAs metal–oxide–semiconductor field-effect-transistors with TiN gate and Ga2O3(Gd2O3) dielectric

A self-aligned process for fabricating inversion n-channel metal–oxide–semiconductor field-effect-transistors (MOSFET’s) of strained In_0.2Ga_0.8As on GaAs using TiN as gate metal and Ga₂O₃(Gd₂O₃) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at V_g = 4 V and V_d = 2 V, a low gate leakage of <10^?7 A/cm² at 1 MV/cm, an extrinsic transconductance of 1.7 mS/mm at V_g = 3 V, V_d = 2 V, and an on/off ratio of ～10⁵ in drain current. For comparison, a TiN/Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10^?8–10^?9 A/cm², well-behaved capacitance–voltage (C–V) characteristics giving a high dielectric constant of ～16 and a low interfacial density of state of ～(2～6) × 10¹¹ cm^?2 eV^?1, and an atomically sharp smooth Ga₂O₃(Gd₂O₃)/In_0.2Ga_0.8As interface.     

Enhanced photocatalytic activity for hydrogen evolution from water by Zn0.5Cd0.5S/WS2 heterostructure

Zn_0.5Cd_0.5S/WS₂ nanocomposites with different amount of Zn_0.5Cd_0.5S solid solution deposited onto the surface of WS₂ were prepared by a one-step hydrothermal method with thioacetamide as sulfur source. Intimate heterojunctions between Zn_0.5Cd_0.5S and WS₂ were identified by TEM and HRTEM technologies in these materials. The chemical composition and valence of the elements were characterized by XPS experiments. The band energies were characterized by UV–vis diffusive reflectance spectroscopy (DRS). The photocatalytic properties of Zn_0.5Cd_0.5S/WS₂ nanocomposites for H₂ evolution from water in the presence of sacrificial reagents were tested. The highest rate of H₂ evolution achieved for these hybrid materials under visible-light irradiation (λ≥420 nm) is about 6 times higher than that of pristine Zn_0.5Cd_0.5S. The promoted catalytic activity of this hybrid material can be ascribed to the formation of the heterojunctions between Zn_0.5Cd_0.5S and WS₂, which enhanced the separation of the photogenerated hole-electron pairs.     

Photovoltaic response of Cu2O/In2S3 hetero-structure grown on Cu substrate

A thin layer of p-type Cu₂O was grown over flexible 30 μm thick copper substrates. Using Injection Chemical Vapor Deposition technique, n-type In₂S₃ thin films were grown over the Cu₂O layer. A p–n junction was thus realized. The Cu₂O/In₂S₃ hetero-structure showed photovoltaic behavior. A solar cell with the structure Cu/Cu₂O/In₂S₃/Ag could be fabricated. An acidic texturization sequence was developed which increased the photo-sensitivity of the In₂S₃ window layer. The Cu/Cu₂O/In₂S₃/Ag hetero-structure with the textured window layer had an open circuit voltage of 377 mV, short circuit current density of 0.118 mA/cm² and fill factor of 33.34%. It was found that the efficiency of the solar cell depended upon the photo-sensitivity of the In₂S₃ window layer. The work demonstrates the use of copper substrate for thin film solar cell fabrication.     

Influence of substrate type on the structural,optical and electrical properties of CdxZn1−xS MSM thin films prepared by Spray Pyrolysis method

0.25 μm Cd_xZn_1−xS thin films were deposited on Si and glass substrates by using a chemical Spray Pyrolysis technique (CSP). Measurements of the absorption spectrum of the film were carried out. The values of band gaps (E_g) are calculated from the absorption spectrum. X-ray diffraction (XRD) of the Cd_xZn_1−xS thin films on Si and glass substrates was carried out. The full width at half-maximum (FWHM)) of diffraction peak was calculated to be about 0.640, which showed that it is a polycrystalline thin film. A Cd_xZn_1−xS Metal–Semiconductor–Metal (MSM) photodetector with nickel (Ni) contact electrodes was then fabricated. The electrical property of the Ni/Cd_xZn_1−xS/Si and Ni/Cd_xZn_1−xS/glass detectors was investigated using the current–voltage (I–V) measurements. The barrier heights ϕ_Β of Ni/Cd_xZn_1−xS/Ni MSM on Si and glass substrates were 0.551 eV and 0.593 eV, respectively with an applied bias voltage of 3 V.     

Sb2(SxSe1−x)3 sensitized solar cells prepared by solution deposition methods

Solid state semiconductor sensitized solar cells are a very active research subject in emerging photovoltaic technologies. In this work, heterojunctions of antimony sulfide-selenide (Sb₂(S_xSe_1−x)₃) solid solution as the absorbing material and cadmium sulfide coated titanium dioxide (TiO₂/CdS) as the electron conductor have been developed with solution deposition methods such as spin-coating, successive ionic layer adsorption and reaction (SILAR), and chemical bath deposition. In particular, CdS has been deposited on mesoporous TiO₂ layers by SILAR deposition, followed by the chemical deposition of Sb₂(S_xSe_1−x)₃. It was found that by increasing the number of CdS SILAR deposition, both the open circuit voltage V_oc and the short circuit current density J_sc of the Sb₂(S_xSe_1−x)₃ sensitized solar cells had been increased from 153 to 434 mV and 0.77–9.73 mA/cm², respectively. This improvement was attributed to the fact that the presence of the CdS on TiO₂ surface reduces the formation of undesired Sb₂O₃ and promotes a better nucleation of the Sb₂(S_xSe_1−x)₃ during the chemical bath deposition. The best result was obtained for the solar cell with 30 cycles of CdS which produced a V_oc of 434 mV, a J_sc of 9.73 mA/cm², and a power conversion efficiency of 1.69% under AM1.5 G solar radiation.     

MISFET structures with barium titanate as a dielectric layer for application in memory cells

This work shows investigations of La₂O₃ containing BaTiO₃ thin films deposited on Si substrates by Radio Frequency Plasma Sputtering (RF PS) of sintered BaTiO₃ + La₂O₃ (2 wt.%) target. Round, aluminum (Al) electrodes were evaporated on top of the deposited layers. Thus, metal–insulator–semiconductor (MIS) structures were created with barium titanate thin films playing the role of an insulator. The MIS structures enabled a subsequent electrical characterization of the studied film by means of current–voltage (I–V) and capacitance–voltage (C–V) measurements. Several electronic parameters, i.e., ε_ri, ρ, V_FB, ΔV_H were extracted from the obtained characteristics. Moreover, the paper describes technology process of MISFETs fabrication and possibility of their application as memory cells. The influence of voltage stress on transfer and output I–V characteristics of the transistors are presented and discussed.     

Properties of In2O3 films obtained by thermal oxidation of sprayed In2S3

In₂S₃ thin films were grown by the chemical spray pyrolysis (CSP) method using indium chloride and thiourea as precursors at a molar ratio of S:In=2.5. The deposition was carried out at 350 °C on quartz substrates. The film thickness is about 1 µm. The films were then annealed for 2 h at 550, 600, 650 and 700 °C in oxygen flow. This process allows the transformation of nanocrystal In₂O₃ from In₂S₃ and the reaction is complete at 600 °C. X-ray diffraction spectra show that In₂O₃ films are polycrystalline with a cubic phase and preferentially oriented towards (222). The film grain size increases from 19 to 25 nm and RMS values increase from 9 to 30 nm. In₂O₃ films exhibit transparency over 70–85% in the visible and infrared regions due to the thickness and crystalline properties of the films. The optical band gap is found to vary in the range 3.87–3.95 eV for direct transitions. Hall effect measurements at room temperature show that resistivity is decreased from 117 to 27 Ω cm. A carrier concentration of 1×10¹⁶ cm^?3 and mobility of about 117 cm² V^?1 s^?1 are obtained at 700 °C.     

Characteristics of RF reactive sputter-deposited Pt/SiO2/n-InGaN MOS Schottky diodes

All RF sputtering-deposited Pt/SiO₂/n-type indium gallium nitride (n-InGaN) metal–oxide–semiconductor (MOS) diodes were investigated before and after annealing at 400 °C. By scanning electron microscopy (SEM), the thickness of Pt, SiO_2, n-InGaN layer was measured to be ~250, 70, and 800 nm, respectively. AFM results also show that the grains become a little bigger after annealing, the surface topography of the as-deposited film was smoother with the rms roughness of 1.67 nm and had the slight increase of 1.92 nm for annealed sample. Electrical properties of MOS diodes have been determined by using the current–voltage (I–V) and capacitance–voltage (C–V) measurements. The results showed that Schottky barrier height (SBH) increased slightly to 0.69 eV (I–V) and 0.82 eV (C–V) after annealing at 400 °C for 15 min in N₂ ambient, compared to that of 0.67 eV (I–V) and 0.79 eV (C–V) for the as-deposited sample. There was the considerable improvement in the leakage current, dropped from 6.5×10⁻⁷ A for the as-deposited to 1.4×10⁻⁷ A for the 400 °C-annealed one. The annealed MOS Schottky diode had shown the higher SBH, lower leakage current, smaller ideality factor (n), and denser microstructure. In addition to the SBH, n, and series resistance (R_s) determined by Cheungs׳ and Norde methods, other parameters for MOS diodes tested at room temperature were also calculated by C–V measurement.     

Carrier transport mechanisms and photovoltaic properties of Au/p-ZnPc/Al device

The dark current density–voltage characteristic of Au/ZnPc/Al device at room temperature has been investigated. Results showed a rectification behavior. At low forward bias, the current density was found to be ohmic, while at high voltages, space charge limited the current mechanism dominated by exponential trapping levels. Junction parameters such as rectification ratio (RR), series resistance (R_s), and shunt resistance (R_sh) were found to be 9.42, 9.72 MΩ, and 0.88 × 10³ MΩ, respectively. The current density–voltage characteristics under white light illumination (100 W/m²) gives values of 0.55 V, 3 × 10⁻³ A/m², 0.18 and 5.8 × 10⁻⁴% for the open circuit voltage, V_oc, the short circuit current density (J_sc), the fill factor (FF), and conversion efficiency (η), respectively.     

Effects of ammonia concentration on property of Cd1−xZnxS films by chemical bath deposition

Cd_1−xZn_xS thin films were grown on soda–lime glass substrates by chemical-bath deposition (CBD) at 80 °C with stirring. All the samples were annealed at 200 °C for 60 min in the air. The crystal structure, surface morphology, thickness and optical properties of the films were studied with transmission electron microscopy (TEM), X-ray diffraction (XRD), scanning electron microscopy (SEM), step height measurement instrument and spectrophotometer respectively. The results revealed that Cd_1−xZn_xS thin films had cubic crystal structure and the intensity of the diffraction peak increased gradually as ammonia concentration rose and the grain size varied from 5.1 to 8.3 nm. All of Cd_1−xZn_xS thin films had a granular surface with some smaller pores and the average granule sizes increased from 92 to 163 nm with an increase in ammonia concentration. The Cd_1−xZn_xS thin films had the highest transmittance with ammonia concentration of 0.5 M L⁻¹, whose thickness was 50 nm and band gap was 2.62 eV.     

The effects of thermal annealing on the electrical characteristics of Au/n–InP/In diode

An Au/n–InP/In diode has been fabricated in the laboratory conditions and the current–voltage (I–V) and capacitance–voltage (C–V) characteristics of the diode have been measured in room temperature. In order to observe the effect of the thermal annealing, this diode has been annealed at temperatures 100 and 200 °C for 3 min in N₂ atmosphere. The characteristic parameters such as leakage current, barrier height and ideality factor of this diode have been calculated from the forward bias I–V and reverse bias C–V characteristics as a function of annealing temperature. Also the rectifying ratio of the diode is evaluated for as-deposited and annealed diode.     

Electrical characterization of solid-state heterojunctions between PEDOT:PSS and an anionic polyelectrolyte

Stable organic heterojunctions are developed by deposition of the anionic polyelectrolyte poly(4-lithium styrenesulfonic acid) (LiPSSA) on the top of poly(3,4-ethylendioxythiophene)/poly(styrenesulfonate) (PEDOT:PSS) films. The electrical response of the heterojunctions to triangular voltage pulses in the range between −5 and +5 V is characterized by hysteresis phenomena, observed for hundreds of cycles with low distortions, at scan rates between 1 and 100 mV/s. The hysteresis is ascribed to the occurrence of redox transitions, evidenced by the presence of well-defined peaks in the current–voltage characteristics. The electrical behaviour of the PEDOT:PSS/LiPSSA devices is found to be mainly capacitive, and show humidity-sensitive functionality, demonstrated by the gradual and reversible increase of the area subtended by the J−V cycles as the relative humidity increases.     

Source/drain metallization effects on the specific contact resistance of indium tin zinc oxide thin film transistors

We report on the specific contact resistance of interfaces between thin amorphous semiconductor Indium Tin Zinc Oxide (ITZO) channel layers and different source/drain (S/D) electrodes (Al, ITO, and Ni) in amorphous oxide thin film transistors (TFTs) at different channel lengths using a transmission line model. All the contacts showed linear current–voltage characteristics. The effects of different channel lengths (200–800 μm, step 200 μm) and the contact resistance on the performance of TFT devices are discussed in this work. The Al/ITZO TFT samples with the channel length of 200 μm showed metallic behavior with a linear drain current-gate voltage (I_D–V_G) curve due to the formation of a conducting channel layer. The specific contact resistance (ρ_C) at the source or drain contact decreases as the gate voltage is increased from 0 to 10 V. The devices fabricated with Ni S/D electrodes show the best TFT characteristics such as highest field effect mobility (16.09 cm²/V·s), ON/OFF current ratio (3.27×10⁶), lowest sub-threshold slope (0.10 V/dec) and specific contact resistance (8.62 Ω·cm² at V_G=0 V). This is found that the interfacial reaction between Al and a-ITZO semiconducting layer lead to the negative shift of threshold voltage. There is a trend that the specific contact resistance decreases with increasing the work function of S/D electrode. This result can be partially ascribed to better band alignment in the Ni/ITZO interface due to the work function of Ni (5.04–5.35 eV) and ITZO (5.00–6.10 eV) being somewhat similar.     

A comparative study of electrical and optical properties of InN and In0.48Ga0.52N

We present results of our studies concerning electrical and optical properties of In_0.48Ga_0.52N and InN. Hall measurement were carried out at temperatures between T=77 and 300 K. Photoluminescence (PL) spectrum in InN and In_0.48Ga_0.52N. InN has a single peak at 0.77 eV at 300 K. However, the PL in In_0.48Ga_0.52N has two peaks; a prominent peak at 1.16 eV and a smaller peak at 1.55 eV. These two peaks are attributed to Indium segregation corresponding to a high Indium concentration of 48% and a low concentration of 36%. High electric field measurements indicate that drift velocity that tends to saturate at around V_d=1.0×10⁷ cm/s at 77 K in InN at an electric field of F=12 kV/cm. However, in In_0.48Ga_0.52N the I–V curve is almost linear up to an electric field of F=45 kV/cm, where the drift velocity is V_d=1.39×10⁶ cm/s. At applied electric fields above this value a S-type negative differential resistance (NDR) is observed leading to an instability in the current and to the irreversible destruction of the sample.     

Frequency and voltage dependency of interface states and series resistance in Al/SiO2/p-Si MOS structure

The capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Al/SiO₂/p-Si metal-oxide-semiconductor (MOS) Schottky diodes have been measured in the voltage range from ?3 to +3 V and frequency range from 5 KHz to 1 MHz at room temperature. It is found that both C and G/ω of the MOS capacitor are very sensitive to frequency. The fairly large frequency dispersion of C–V and G/ω–V characteristics can be interpreted in terms of the particular distribution of interface states at SiO₂/Si interface and the effect of series resistance. At relatively low frequencies, the interface states can follow an alternating current (AC) signal that contributes to excess capacitance and conductance. This leads to an anomalous peak of C–V curve in the depletion and accumulation regions. In addition, a peak at approximately ?0.2 V appears in the R_s–V profiles at low frequency. The peak values of the capacitance and conductance decrease with increasing frequency. The density distribution profile of interface state density (N_ss) obtained from C_HF–C_LF capacitance measurement also shows a peak in the depletion region.     

Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process has been fabricated by integration of polysilicon-filled trenches. We have simulated its electrical characteristics by using TCAD software and compared them with results obtained from electrical measurements. The threshold voltage and the subthreshold slope of the top gate have been extracted and we found a good accordance, for both parameters, between the measurements (V_TH=0.59 V, S=90 mV/dec) and simulations (V_TH=0.50 V, S=92 mV/dec). The surface channel effective mobility of this multi-gate MOSFET was extracted and evaluated with both effective length and surface. The studies revealed that mobility degraded towards smaller dimensions of the MOS channel. At last, the Si/SiO₂ interface quality studies were carried out. We noticed that the injected donor traps have a larger influence on the current–voltage characteristics than acceptor-like traps. With its good electrical performances, this low-cost multi-gate MOSFET technology presents interesting perspective in CMOS image sensors and more generally in analog application taking benefit of the multi-threshold for example.     

Direct synthesis of quaternary Cd(Zn,S)Se thin films: Effects of composition

In the present communication, the binary CdSe and quaternary Cd_1-xZn_xSe_1-yS_y (0 ≤ x = y ≤ 0.35) thin films were synthesized using a chemical bath deposition. Thin film deposition was carried out at the optimized conditions (pH = 10 ± 0.1, deposition temperature = 70 ± 0.1 °C, deposition time = 100 min and substrate rotation speed = 65 ± 2 rpm). X-ray diffraction studies confirmed hexagonal-wurtzite crystal structure with the formation of quaternary Cd(Zn, S)Se phase along with binary CdSe, CdS, ZnS and ZnSe, phases of the as-grown Cd_1-xZn_xSe_1-yS_y thin films. Elemental analysis showed presence of Cd²⁺, Zn²⁺, S^2- and Se^2- in the deposited films. Fourier transform infrared spectroscopy shown the bands at 911.15 cm⁻¹ – 901.62 cm⁻¹ which are assigned to the stretching frequency of Cd–Se bond. Scanning electron microscopy show transformation of the microstructure from globular crystallites to a rhomboid flake like network. The electrical conductivity was typically ≈ 10⁻⁷ Ω⁻¹ cm⁻¹. At low temperatures, the conduction was by variable range hopping, and this changed to thermally activated grain boundary dominated conduction for T > 350 K.     

Current–voltage and capacitance–voltage characteristics of Al Schottky contacts to strained Si-on-insulator in the wide temperature range

The electrical characteristics of Al/strained Si-on-insulator (sSOI) Schottky diode have been investigated using current–voltage (I–V) and capacitance–voltage (C–V) measurements in the wide temperature range of 200–400 K in steps of 25 K. It was found that the barrier height (0.57–0.80 eV) calculated from the I–V characteristics increased and the ideality factor (1.97–1.28) decreased with increasing temperature. The barrier heights determined from the C–V measurements were higher than those extracted from the I–V measurements, associated with the formation of an inhomogeneous Schottky barrier at the interface. The series resistance estimated from the forward I–V characteristics using Cheung and Norde methods decreased with increasing temperature, implying its strong temperature dependence. The observed variation in barrier height and ideality factor could be attributed to the inhomogeneities in Schottky barrier, explained by assuming Gaussian distribution of barrier heights. The temperature-dependent I–V characteristics showed a double Gaussian distribution with mean barrier heights of 0.83 and 1.19 eV and standard deviations of 0.10 and 0.16 eV at 200–275 and 300–400 K, respectively. From the modified Richardson plot, the modified Richardson constant were calculated to be 21.8 and 29.4 A cm⁻² K⁻² at 200–275 and 300–400 K, respectively, which were comparable to the theoretical value for p-type sSOI (31.6 A cm⁻² K⁻²).