Performance and reliability of low-temperature polysilicon TFT with a novel stack gate dielectric and stack optimization using PECVD nitrous oxide plasma

This paper proposes a novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si thin-film transistors, composed of a plasma-enhanced chemical vapor deposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N/sub 2/O plasma. The novel stack gate dielectric exhibits a very high electrical breakdown field of 8.5 MV/cm, which is approximately 3 MV/cm higher than traditional PECVD TEOS oxide. The novel stack oxide also has better interface quality, lower bulk-trap density, and higher long-term reliability than PECVD TEOS dielectrics. These improvements are attributed to the formation of strong Si/spl equiv/N bonds of high quality ultra-thin oxynitride grown by PECVD N/sub 2/O plasma, and the reduction in the trap density at the oxynitride/poly-Si interface.     

Particle control in dielectric etch chamber

A methodology for evaluating and controlling particle performance in a dielectric etch system is developed and presented. Analysis of particle samples, collected from premature chamber failures for out-of-control particle levels, suggests sputtering of the upper electrode during etching is a key modulator to this problem. To eliminate such sputtering, we designed a series of experiments with the objective of identifying a between-lot conditioning (BLC) process capable of creating a uniform and solid layer of polymer coating that covers the entire upper electrode of a parallel plate, RF, magnetically enhanced reactive ion etch system. An approach comprising a series of short wafer processing marathon runs, with polymer coverage and particle performance as the two main responses, was then used to identify a candidate process for BLC recipe and usage frequency. Adequate non flaking polymer coverage of the upper electrode was achieved by utilizing a BLC process based on octafluoro-cyclobutane/oxygen/argon/carbonmonoxide [C/sub 4/F/sub 8//O/sub 2//Ar/CO] chemistry at high RF power and short transit time settings. The candidate process was then optimized and tested in a manufacturing pilot involving multiple production etch chambers and was subjected to extensive process performance metrics. Based on this methodology, the optimized BLC was successful in controlling defects and in attaining the mean wafer between wet clean goal for the etch system under investigation.     

Investigation of hole-tunneling current through ultrathinoxynitride/oxide stack gate dielectrics in p-MOSFETs

The systematic investigation of hole tunneling current through ultrathin oxide, oxynitride, oxynitride/oxide (N/O) and oxide/oxynitride/oxide (ONO) gate dielectrics in p-MOSFETs using a physical model is reported for the first time. The validity of the model is corroborated by the good agreement between the simulated and experimental results. Under typical inversion biases (|VG|<2 V), hole tunneling current is lower through oxynitride and oxynitride/oxide with about 33 at.% N than through pure oxide and nitride gate dielectrics. This is attributed to the competitive effects of the increase in the dielectric constant, and hence dielectric thickness, and decrease in the hole barrier height at the dielectric/Si interface with increasing with N concentration for a given electrical oxide thickness (EOT). For a N/O stack film with the same N concentration in the oxynitride, the hole tunneling current decreases monotonically with oxynitride thickness under the typical inversion biases. For minimum gate leakage current and maintaining an acceptable dielectric/Si interfacial quality, an N/O stack structure consisting of an oxynitride layer with 33 at.% N and a 3 Å oxide layer is proposed. For a p-MOSFET at an operating voltage of -0.9 V, which is applicable to the 0.7 μm technology node, this structure could be scaled to EOT=12 Å if the maximum allowed gate leakage current is 1 A/cm² and EOT=9 Å if the maximum allowed gate leakage current is 100 A/cm²     

Characterization and optimization of metal etch processes tominimize charging damage to submicron transistor gate oxide

Two metal etch systems are compared in terms of their impacts on submicron transistor gate oxide integrity. The magnetically enhanced RIE (MERIE) system is shown to cause significant gate oxide damage with a pronounced radial dependence. This damage does not occur on wafers etched in the hexode-type RIE system. Experimental work on the MERIE system shows that the presence of the magnetic field during the aluminum overetch and barrier metal etch portion of the process is the primary cause for the observed gate oxide damage. This damage can be minimized by reducing or eliminating the magnetic field during the overetch step     

Abnormal metal oxide formation induced by residual charging in plasma etch process

Electron cyclotron resonance plasma with SF₆ and Cl₂ gas mixture were used for tungsten plug etch-back processes. The properties of electric contacts between tungsten plugs and Al/Ti/TiN interconnect lines, fabricated by this etching process, have been studied. Particles and abnormal oxide layers at the plug/line interfaces have been found to be the main factor to cause deterioration of the electric contacts. Mechanisms for particle transportation and metal oxide formation have been proposed. The phenomenon was attributed to the residual charging effect, which occurred immediately after the plasma power being turned off. A technique to prevent the residual charging induced tungsten oxide growth has been developed and applied in industrial fabrication lines.     

超薄氧化门的等离子体充电损伤机理

探讨了金属氧化物半导体场效应管超薄氧化门在等离子体加工中造成的充电损伤机理,应用碰撞电离模型解释了超薄氧化门对充电损伤比厚氧化门具有更强免疫力的原因.     

ECR plasma etch fabrication of C-doped base InGaAs/InP DHBT structures: A comparison of CH4/H2/Ar vs BCl3/N2 plasma etch chemistries

We compare ECR plasma etch fabrication of self-aligned thin emitter carbondoped base InGaAs/InP DHBT structures using either CH₄/H₂/Ar or BCl₃/N₂ etch chemistries. Detrimental hydrogen passivation of the carbon doping in the base region of our structure during CH₄/H₂/Ar dry etching of the emitter region is observed. Initial conductivity is not recovered with annealing up to a temperature of 500°C. This passivation is not due to damage from the dry etching or from the MOMBE growth process, since DHBT structures which are ECR plasma etched in BCl₃/N₂ have the same electrical characteristics as wet etched controls. It is due to hydrogen implantation from the plasma exposure. This is supported with secondary ion mass spectroscopy profiles of structures which are etched in CH₄/D₂/Ar showing an accumulation of deuterium in the C-doped base region.     

CMOS gate oxide defects induced by pre-gate plasma process

Plasma processes used for strip resist and etch oxide in CMOS technologies may degrade the quality of the silicon surface if it is protected of the plasma by a too thin oxide capping. Using AFM measurements, we have identified this degradation as a silicon roughness increase. The degradation mechanism can be understood like an uncontrolled plasma oxidation of the silicon. Next, if gate oxidation is performed after such plasma treatments, the gate oxide will show defects at the oxide/silicon interface. The consequence will be a poor reliability when negative electrical bias is applied on CMOS gate. Finally, the damaged silicon layer can also be efficiently removed by performing a sacrificial oxidation.     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

Some issues in advanced CMOS gate stack performance and reliability

This paper summarizes and analyzes some of our previous works on the advanced gate stacks for CMOS transistors focused on the following two topics: 1. Frequency dependence of Dynamic Bias Temperature Instability (DBTI) and the transistor degradation mechanism, 2. A novel way for metal gate Effective Work Function (EWF) modulation by incorporation of lanthanum elements in HfO₂ gate dielectric.     

Monitoring and diagnosis of plasma etch processes

Plasma etching removes material from a silicon wafer by applying power and gases in a chamber. As material is removed from a wafer, the amount of particular chemicals given off can be measured; this technique is called emission spectroscopy and the measurements are called endpoint traces. An expert system that automatically interprets the traces has been designed and built. The system combines signal-to-symbol transformations for data abstraction and rule-based reasoning for diagnosis. The system detects problems as soon as they occur and also determines their causes     

Impact strain engineering on gate stack quality and reliability

Strain engineering based on either a global approach using high-mobility substrates or the implementation of so-called processing-induced stressors has become common practice for 90 nm and below CMOS technologies. Although the main goal is to improve the performance by increasing the drive current, other electrical parameters such as the threshold voltage, the multiplication current, the low frequency noise and the gate oxide quality in general may be influenced. This paper reviews the impact of different global and local strain engineering techniques on the gate stack quality and its reliability, including hot carrier performance, negative bias temperature instabilities, time dependent dielectric breakdown and radiation hardness. Recent insights will be discussed and the influence of different strain engineering approaches illustrated.     

Influence of low-k dry etch chemistries on the properties of copper and a Ta-based diffusion barrier

In this study, the film properties of Cu and a Ta-based diffusion barrier deposited on organic polymer and SSQ-based low-k materials with subtractive porosity were investigated. Emphasis was put on the effects of exposure of the low-k materials to the dry etch plasmas prior to metal deposition. The metal film properties were influenced by the type of the dry etch plasma chemistry used and by the porosity of the low-k material. Thermal desorption spectra (TDS) obtained during annealing of these metal films revealed an increased amount of species with m/e 44, attributed to CO₂, and H₂O desorbing from the Cu film at high temperatures. The TDS data for the Ta film did not contain such high temperature desorption peaks for these species mentioned. Surface morphology of the Cu and Ta films observed by scanning electron microscopy (SEM) and atomic force microscopy (AFM) also showed a poor wetting of the metal films on the porous low-k materials that have been dry etch plasma treated.     

Prediction of plasma charging induced gate oxide damage by plasmacharging probe

The plasma processing induced wafer charging damage is predicted by the newly developed SPORT (Stanford Plasma On-wafer Real Time) charging probe. Such a probe can directly measure the spatial charging voltage built up on a wafer surface as well as the charging current from the plasma. Both antenna dependence of damage and charge fluence through a gate oxide due to charging can be calculated from the intersection between plasma I-V characteristic measured by the probe and intrinsic MOS I-V characteristic. This result agrees well with the real MOS capacitor damage data from O₂ plasma processing. Thus, given a fluence criteria, this methodology gives a means for predicting the minimum antenna ratio for observable damage     

Investigation of inductively coupled plasma gate oxide on lowtemperature polycrystalline-silicon TFTs

By optimizing the inductively coupled plasma (ICP) oxidation condition, a thin oxide of 10 nm has been grown at 350°C to achieve excellent gate oxide integrity of low leakage current<5×10^-8 A/cm² (at 8 MV/cm), high breakdown field of 9.3 MV/cm and low interface trap density of 1.5×10¹¹ /eV cm². The superior performance poly-Si TFTs using such a thin ICP oxide were attained to achieve a high ON current of 110 μA/μm at V_D=1 V and V_G=5 V and the high electron field effect mobility of 231 cm²/V·S     

Supervisory run-to-run control of polysilicon gate etch using insitu ellipsometry

Polysilicon gate etch is a critical manufacturing step in the manufacturing of MOS devices because it determines the tolerance limits on MOS circuit performance. The etch used in the current study suffers from machine aging, which causes processing results to drift with time. Performing the etch for the same time with fixed process setpoints (recipe) for all wafers would produce unsatisfactory results. Thus, an in situ ellipsometer was employed with a new run-to-run supervisory controller, termed predictor corrector control (PCC), to eliminate the impact of machine and process drift. A novel modeling technique was used to predict uniformity from the ellipsometry data collected at a single site on the wafer. Predictive models are employed by the PCC supervisory controller to generate optimal settings (recipe) for every wafer which will achieve a target mean etch rate, while maintaining a spatially uniform etch. A 200 wafer experiment was conducted to demonstrate the benefits of process control. Implementation of PCC resulted in a 36% decrease in standard deviation from target for the mean etch rate. In addition, the data indicates that controlling etch rate may improve the control and uniformity of the line width change     

Effects of boron diffusion in pMOSFETs with TiN-HfSiO gate stack

Boron diffusion in TiN-HfSiO gate stack capped with polysilicon layer has been studied. SIMS analysis indicates that a significant amount of B diffused from B-doped polysilicon through TiN layer into nitrided HfSiO gate dielectrics. Grain boundaries in TiN thin film are considered a conduit of B into HfSiO. Even though most of B was stopped within HfSiO film owing to N incorporation, significant V/sub t/ shift and interface properties degradation were observed. It was found that B in HfSiO serves as positive charge and shifts pMOSFET V/sub t/ to negative side.     

Statistical experimental design in plasma etch modeling

The objective of this work is to obtain a comprehensive set of empirical models for plasma etch rates, uniformity, selectivity, and anisotropy. These models accurately represent the behavior of a specific piece of equipment under a wide range of etch recipes, thus making them ideal for manufacturing and diagnostic purposes. The response characteristics of a CCl₄-based plasma process used to etch doped polysilicon were examined via a 2^6-1 fractional factorial experiment followed by a Box-Wilson design. The effects of variation in RF power, pressure, electrode spacing, CCl₄ flow, He flow and O₂ flow on several output variables, including etch rate, selectivity, and process uniformity, were investigated. Etch anisotropy was also measured by scanning electron microscopy analysis on a 2^6-2 fraction of the original experiment. The screening factorial experiment was designed to isolate the most significant input parameters. Using this information as a platform from which to proceed, the subsequent phase of the experiment allowed the development of empirical models of etch behavior using response surface methodology (G. E. P. Box and N. D. Draper, 1987). The models were subsequently used to optimize the etch process     

Optimization of gate stack parameters towards 3D-SONOS application

A planar SONOS capacitor was used to optimize different parameters of the gate stack, in view of integration in a 3D cell. It is found that a poly-Si substrate strongly degrades the channel mobility but program and retention are not compromised. The ONO stack is found to scale down to 3/4/5 nm for tunnel oxide/trapping nitride/blocking oxide, respectively. FUSI gate could be an interesting option to improve the erase operation.     

Hydrogen sensitivity of InP HEMTs with WSiN-based gate stack

We have experimentally investigated the hydrogen sensitivity of InP high-electron mobility transistors (HEMTs) with a WSiN-Ti-Pt-Au gate stack. We have found that exposure to hydrogen produces a shift in the threshold voltage of these devices that is one order of magnitude smaller than published data on conventional Ti-Pt-Au gate HEMTs. We have studied this markedly improved reliability through a set of quasi-two-dimensional mechanical and electrostatic simulations. These showed that there are two main causes for the improvement of the hydrogen sensitivity. First, the separation of the Ti-layer from the semiconductor by a thick WSiN layer significantly reduces the stress in the heterostructure underneath the gate. Additionally, the relatively thinner heterostructure used in this study and the presence of an InP etch-stop layer with a small piezoelectric constant underneath the gate reduces the amount of threshold voltage shift that is caused by the mechanical stress.