直拉硅单晶中的流动图形缺陷

用Secco腐蚀液对直径15 0 mm p型(10 0 )直拉硅单晶片进行择优腐蚀后,得到了流动图形缺陷(FPDs) ,并通过原子力显微镜(AFM)对其微观结构进行观察.实验发现,在FPDs缺陷的尖端存在有几百纳米的由(111)面构成的八面体空洞,这与Takeno等人的实验结果相反,他们认为FPD的端部是间隙型的位错环;实验还发现,FPD端部的空洞随腐蚀时间延长会逐渐变为圆形的浅坑直至最后消失     

Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H₂SO₄, 96%) and hydrogen peroxide (H₂O₂, 30%), 120 °C), SC1 (1:1:5 mixture of NH₄OH, H₂O₂ and H₂O, at 80 °C) or HF solution (6 parts of 40% NH₄F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film.     

Texturization of silicon wafers with Na2CO3 and Na2CO3/NaHCO3 solutions for heterojunction solar-cell applications

The formation of pyramidal structures by anisotropic etching of 〈1 0 0〉-oriented monocrystalline silicon wafer surfaces is an effective method to reduce reflection losses originating on the front side of conventional silicon solar cells and silicon-heterojunction (SHJ) solar cells. One of the most common methods of texturization used in the solar-cell industry is based on aqueous solutions of NaOH or KOH and isopropyl alcohol (IPA). However, IPA is toxic and relatively expensive, so efforts are being made to replace it. Among the potential alternatives, solutions based on Na₂CO₃ and Na₂CO₃/NaHCO₃ mixtures have been proposed. In the present study, solutions of Na₂CO₃ and Na₂CO₃/NaHCO₃ mixtures were prepared in order to form pyramidal structures on silicon wafer surfaces. It was not possible to obtain uniform and completely textured surfaces by using aqueous solutions consisting only of Na₂CO₃. NaHCO₃ must be added in order to achieve uniform textured surfaces with low hemispherical reflectance suitable for SHJ solar-cell applications. Textured surfaces with good uniformity and low average hemispherical reflectance (15.4%) were prepared from 〈1 0 0〉 silicon substrates with relatively low etching times (25 min). Good surface passivation (lifetime >600 μs and implicit open-circuit voltage of 690±10 mV) on these p-type textured wafers were achieved.     

A chromium-free etchant for delineation of defects in heavily doped n-type silicon wafers

Delineation of defects in the heavily doped n-type Czochralski silicon wafers by preferential etching is an issue not having been essentially solved. Herein, a chromium-free etchant based on HNO₃–HF–H₂O system, with an optimum volume ratio of V_HNO3%:V_HF%:V_H2O%=20%:45%:35%, has been developed. It can reveal well the defects such as dislocation and oxygen precipitation-induced bulk microdefects (BMDs) in the heavily doped n-type silicon wafers with resistivities even lower than 1 mΩ cm. Moreover, this etchant is appropriate to delineate the defects on (1 1 1), (1 1 0) or (1 0 0) surface of silicon crystal. Furthermore, the density of oxygen precipitation-induced BMDs in the heavily doped n-type silicon wafers derived from the preferential etching using this newly developed etchant correlates well with that derived from scanning infrared microscopy (SIRM) within its detection limit.     

Characteristics of ZnOV2O5MnO2Nb2O5Er2O3 semiconducting varistors with sintering processing

The effects of sintering temperature on the microstructure, electrical properties, and dielectric characteristics of ZnOV₂O₅MnO₂Nb₂O₅Er₂O₃ semiconducting varistors have been studied. With increase in sintering temperature the average grain size increased (4.5–9.5 μm) and the density decreased (5.56–5.45 g/cm³). The breakdown field decreased with an increase in the sintering temperature (6214–982 V/cm). The samples sintered at 900 °C exhibited remarkably high nonlinear coefficient (50). The donor concentration increased with an increase in the sintering temperature (0.60×10¹⁸–1.04×10¹⁸ cm^?3) and the barrier height exhibited the maximum value (1.15 eV) at 900 °C. As the sintering temperature increased, the apparent dielectric constant increased by more than four-fold.     

Formation and characterization of porous silicon films obtained by catalyzed vapor-chemical etching

Porous silicon films obtained by the metal-assisted vapor-chemical etching technique have been characterized. For the film formation, epitaxial (100) N/P⁺, 1–5 Ω cm monocrystalline silicon wafers were used. The vapors of an alcoholic solution of H₂O₂/HF were drawn towards the silicon surface, which was previously covered with a thin layer of gold (~8 nm) for the catalytic etching. For the optical and morphological characterization of porous films, Raman spectroscopy, Ellipsometry, FTIR spectroscopy and SEM images were used. The films thickness kept a linear relationship with etching time. A porosity gradient from the surface towards the interface (65% to 12%) was observed in the films. A large amount of Si–H bonds as related to O–Si–O bonds were observed and the pore size depends on the HF concentration. Irregular morphology was found in films formed with 50% HF.     

Surface integrity and removal mechanism of silicon wafers in chemo-mechanical grinding using a newly developed soft abrasive grinding wheel

A new soft abrasive grinding wheel (SAGW) used in chemo-mechanical grinding (CMG) was developed for machining silicon wafers. The wheel consisted of magnesia (MgO) soft abrasives, calcium carbonate (CaCO₃) additives and magnesium oxychloride bond. Surface topography, roughness and subsurface damage of the silicon wafers ground using the new SAGW were comprehensively investigated. The results showed that the grinding with the new SAGW produced a surface roughness of about 0.5 nm in R_a and a subsurface damage layer of about 10 nm in thickness, which is comparable to that produced by chemo-mechanical polishing. This study also revealed that the chemical reactions between MgO abrasive, CaCO₃ additives and silicon material did occur during grinding, thereby generating a soft reactant layer on the ground surface. The reactant layer was easily removed during the grinding process.     

Surface photovoltage measurements for Cu,Ti and W determination in Si wafers

p-type (1 0 0) Cz silicon wafers were contaminated with Cu, W, and Ti in the dose range of 5×10⁹–1×10¹⁴ cm⁻² by ion implantation. Surface photovoltage measurements were used to detect the metal impurities after annealing. Fast and slow cooling have been used and calibration curves have been obtained in all cases. Higher sensitivity has been determined for slow cooling (Cu and W) or fast cooling (Ti) depending if deep levels are associated with substitutional (Cu and W) or interstitial (Ti) position.     

High-performance pentacene field-effect transistors using Al2O3 gate dielectrics prepared by atomic layer deposition (ALD)

High-performance pentacene field-effect transistors have been fabricated using Al₂O₃ as a gate dielectric material grown by atomic layer deposition (ALD). Hole mobility values of 1.5 ± 0.2 cm²/V s and 0.9 ± 0.1 cm²/V s were obtained when using heavily n-doped silicon (n⁺-Si) and ITO-coated glass as gate electrodes, respectively. These transistors were operated in enhancement mode with a zero turn-on voltage and exhibited a low threshold voltage (< −10 V) as well as a low sub-threshold slope (<1 V/decade) and an on/off current ratio larger than 10⁶. Atomic force microscopy (AFM) images of pentacene films on Al₂O₃ treated with octadecyltrichlorosilane (OTS) revealed well-ordered island formation, and X-ray diffraction patterns showed characteristics of a “thin film” phase. Low surface trap density and high capacitance density of Al₂O₃ gate insulators also contributed to the high performance of pentacene field-effect transistors.     

Bismuth doped ZnSe films fabricated on silicon substrates by pulsed laser deposition

The preparation of bismuth doped ZnSe films on silicon (1 0 0) by pulsed laser deposition (PLD) is reported. Bismuth was used as a p-type dopant source material for ZnSe. The stable p-type films with hole carrier concentration of about 10¹⁶–10¹⁸ cm^?3 were obtained. By scanning electron microscopy (SEM) and X-ray diffraction (XRD), it was found that the ambient pressure during film deposition has much to do with the morphology and crystallinity of the as-deposited products. The presence of Bi in the Bi-doped ZnSe films was confirmed by the X-ray photoelectron spectroscopy (XPS) and the possibility of a Bi_Zn–2V_Zn complex forming a shallow acceptor level was discussed.     

Scaling down of organic complementary logic gates for compact logic on foil

In this work, we realize complementary circuits with organic p-type and n-type transistor integrated on polyethylene naphthalate (PEN) foil. We employ evaporated p-type and n-type organic semiconductors spaced side by side in bottom-contact bottom-gate coplanar structures with channel lengths of 5 μm. The area density is 0.08 mm² per complementary logic gate. Both p-type and n-type transistors show mobilities >0.1 cm²/V s with V_on close to zero volt. Small circuits like inverters and 19-stage ring oscillators (RO) are fabricated to study the static and the dynamic performance of the logic inverter gate. The circuits operate at V_dd as low as 2.5 V and the inverter stage delay at V_dd = 10 V is as low as 2 μs. Finally, an 8 bit organic complementary transponder chip with data rate up to 2.7 k bits/s is fabricated on foil by successfully integrating 358 transistors.     

Fabrication of NbN/AlN/NbN junctions with Al embedding circuits on Si membrane for 1.5 THz SIS mixers

A process has been developed to fabricate NbN tunnel junctions and 1.5 THz SIS mixers with Al electrodes and Al/SiO₂/Al microstrip tuning circuits on thin Si membranes patterned on silicon on insulator wafers (SIMOX). High Josephson current density (J_c up to 2×10⁴ A/cm²) NbN/AlN/NbN and NbN/MgO/NbN SIS junctions have been fabricated with a reasonably good V_m quality factor and energy gap values close to 5 meV at 4.2 K on (100) oriented 3 inches SIMOX wafers covered by a thin (∼8 nm) MgO buffer layer. The sputtering conditions critically influence the dielectric quality of both AlN and MgO tunnel barriers as well as the surface losses of NbN electrodes. 0.6-μm Si/SiO₂ membranes are obtained after processing of a whole wafer and etching the individual chips in EDP. Such a technology is applied to the development of a waveguide/membrane SIS mixer for use around 1.5 THz.     

Influence of deposition pressure on p-type a-Si:H window layer doped by trimethylboron for a-Si:H superstrate solar cell in plasma enhanced chemical vapor deposition

Wide bandgap (E_g) p-type window layer is very important for silicon based thin film solar cell to obtain high performance, especially high open-circuit voltage (V_OC). In this work, the influence of the deposition pressure on the properties of p-type a-Si:H window layer doped by trimethylboron (TMB) in plasma enhanced chemical vapor deposition (PECVD) was investigated systematically by transmission, Raman, and Fourier transform infrared (FTIR) spectroscopies. As a result, high performance hydrogenated amorphous silicon (a-Si:H) p–i–n superstrate solar cell with V_OC up to 927 mV was successfully achieved on Asahi Type-U SnO₂:F coated glass. In this case, excellent wide bandgap p-type a-Si:H window layer was fabricated under a mild deposition condition, including a low hydrogen dilution ratio (H₂/SiH₄) of 20, a relatively high deposition temperature of 220 °C, which was also adopted for the i-layer and n-layer deposition, and a moderate deposition pressure of about 160 Pa. We think it is the compromise between wide E_g and good microstructure quality of the p-layer that brings about the good solar cell performance. Such p-type window layer will be very helpful for the fabrication of a-Si:H solar cell, especially of the cell finished in a single PECVD chamber, due to its mild deposition condition.     

Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate

A novel interface charge islands partial-SOI (ICI PSOI) high voltage device with a silicon window under the source and its mechanism are studied in this paper. ICI PSOI is characterized by a series of equidistant high concentration n⁺-regions on the bottom interface of top silicon layer. On the condition of high-voltage blocking state, inversion holes located in the spacing of two n⁺-regions effectively enhance the electric field of the buried oxide layer (E_I) and reduce the electric field of the silicon layer (E_S), resulting in a high breakdown voltage (V_B). It is shown by the simulations that the enhanced field ΔE_I and reduced field ΔE_S by the accumulated holes reach to 449 V/μm and 24 V/μm, respectively, which makes V_B of ICI PSOI increase to 663 V from 266 V of the conventional PSOI on 5 μm silicon layer and 1 μm buried oxide layer with the same silicon window length. On-resistance of ICI PSOI is lower than that of the conventional PSOI. Moreover, self-heating-effect is alleviated by the silicon window in comparison with the conventional SOI at the same power of 1 mW/μm.     

Temperature dependence of electrical properties for MOS capacitor with HfO2/SiO2 gate dielectric stack

We investigated the temperature dependence of C–V and I–V characteristics in p-type Metal Oxide Semiconductor (MOS) capacitors with HfO₂/SiO₂ dielectric stacks. Dramatic degradation in the C–V characteristics at/over the measurement temperature of 125 °C was observed, which was caused by the increased effective oxide thickness, oxide trapped charge density, and interfacial density of state (D_it) with rising temperature during bias temperature stress. In the accumulation region, the leakage current density displayed strong temperature dependence in the ?3 V<Vg<0 V region, as expected for the direct tunneling compared to the trap-assisted component (DT+TAT) effect. The conduction mechanism was transformed into Fowler–Nordheim (FN) tunneling (weak T and Vg dependence) from DT+TAT (strong T and Vg dependence) at Vg <?3 V, which was confirmed by FN tunneling fitting. According to the conventional Shockley–Read–Hall model, the different levels in D_it were found at various measurement temperatures to interpret the strong temperature dependence and weak Vg dependence inversion current property.     

New insights into acidic wet chemical silicon etching by HF/H2O–NOHSO4–H2SO4 solutions

Acidic wet chemical etching of crystalline silicon has been examined by utilization of HF–NOHSO₄–H₂SO₄ mixtures. In light of our previous studies the effects of nitrosyl ion concentrations on etching rates were studied time- and temperature resolved. The reactivity of crystalline silicon surfaces in HF/H₂SO₄ solutions is determined by NO⁺-ion concentrations at the silicon/electrolyte interface, measured by ion chromatography. Quantitative solution analysis proofed accumulation of ammonium ions and indicated the conversion of NO⁺ as limiting for the overall etching process. Direct participation in the rate-limiting step was confirmed by calculation of activation energies. Increasing NO⁺-ion contents cause transition from reaction (E_A=55 kJ mol^?1) to diffusion controlled (E_A=10 kJ mol^?1) etching procedures. In combination with time and concentration dependent studies of produced structures a convenient regime for selective texturing or polishing polycrystalline silicon surfaces is reported. Qualitative analysis by ¹⁹F-NMR and Raman spectroscopy identified SiF₅^?/HF₂^? complexes as well as elementary hydrogen (H₂) as hitherto unknown products of silicon dissolution reactions in HF–NOHSO₄–H₂SO₄ mixtures. Based on our findings a strategy for fundamental investigations of relevant reaction pathways is presented and discussed with regard to reported mechanistic concepts.     

Bipolar transistor with quantum well base

We report in this study the modeling of a heterostructure bipolar transistor (HBT) where the base is designed as a quantum well. The transistor structure consists of a base layer of GaAs that is heavily p-type doped. The 0.024 μm base is sandwiched between wide band gap In_xGa_1?xP which composes the n-type emitter and collector layers immediately adjacent to the base. The thickness of the base was chosen so that it is comparable to the wavelength of the electrons passing though it. There are two heavily doped cap layers of InGaAs at the emitter contact. The remainder of the emitter and collector regions are composed of GaAs. The purpose of this design is to filter the energies and velocities of electrons as they pass through the base region that forms a quantum barrier to electrons and a quantum well to holes. This should result in a significant decrease of noise in comparison to that observed in non-quantum base HBTs. As expected, the thin quantum well improves the collection of injected carriers, which in turn boosts the DC gain (β) to 750 and increases the power of the novel transistor by a factor of six, in comparison to a commercially available HBT with a similar non-quantum well structure. At high frequencies, the gain of the device is increased by about 5 dB over the non-quantum base HBT that this device is based upon. Additionally, the cutoff frequency is improved from 20 to 50 GHz. Modeling of the novel transistor was done using Silvaco ATLAS?. This study will continue with the fabrication of experimental wafers.     

Physical properties and electrical characteristics of H2O-based and O3-based HfO2 films deposited by ALD

Ozone (O₃) and H₂O are used as the oxidant to deposit hafnium oxide (HfO₂) thin films on p-type Si (1 0 0) wafers by atomic layer deposition (ALD). The physical properties and electrical characteristics of HfO₂ films change greatly for different oxidants and deposition temperature. Compared with O₃ as the oxidant, HfO₂ films grown with H₂O as the oxidant are more consistent in composition and growth rate. The O₃-based HfO₂ films have lower C impurity and higher concentration N impurity than the H₂O-based HfO₂ films. The impact of the annealing process on the electrical properties and stability of HfO₂ films are also investigated. A width step is observed in the O₃-based HfO₂ C–V curves, which disappears after annealing process. It is because the unstable Hf–O–N and Hf–N bonds in O₃-based HfO₂ films are re-bonded with the non-HfO₂ oxygen after annealing process, and the binding energy of N_1s shifts.     

High power impulse magnetron sputtered p-type γ-titanium monoxide films: Effects of substrate bias and post-annealing on microstructure characteristics and optoelectrical properties

In view of wide potential use as p-type oxide semiconductor of titanium monoxide (TiO), it is deposited in this work by using high power impulse magnetron sputtering (HIPIMS), which is known to provide less hysteresis effect in reactive sputtering and better control in stoichiometry. A strong correlation among the preparation parameters on the microstructure and optoelectrical characteristics of the obtained Ti-O films are investigated.Experimental results show that the crystallinic cubic γ-TiO can be directly grown on unheated glass substrate. In regard to the effects of substrate bias and post-annealing, the as-grown γ-TiO transfers into rutile (R-TiO₂) at a critical substrate bias voltage of −125 V or post-annealing temperature of 500 °C. For the purpose of p-type channel layer in transistor, the optimum γ-TiO film exhibiting a high hole mobility of 8.2 cm²/V s is grown at the substrate bias voltage of −25 V and followed by the post-annealing at 400 °C.