Hybrid dual gate ferroelectric memory for multilevel information storage

Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200 °C), and demonstrate excellent performance with high hole mobility of 2.7 cm² V⁻¹ s⁻¹, large memory window of ∼18 V, and a low sub-threshold swing ∼−4 V dec⁻¹. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.     

Theoretical analysis of high-k dielectric gate stacks

Density functional theory (DFT) has proved to be a useful tool in engineering of emerging research devices. At the nanoscale, and particularly when novel materials are involved, it provides not only the fundamental understanding of the microscopic physics governing the behavior of a system, but often can give quantitative results that can be directly used in process development. In this paper we briefly review the recent applications of DFT in the area of the advanced gate stack materials engineering     

A novel approach to characterization of progressive breakdown in high-k/metal gate stacks

Dielectric breakdown (BD) of nFETs with TiN metal gates and HfO₂/interfacial layer with 1.09 nm EOT is studied. Occurrence of progressive BD at low current levels is demonstrated. A new measurement methodology for extraction of the PBD time and its dependence on gate voltage are reported.     

Electrical characterization of directly deposited La-Sc oxides complex for gate insulator application

This study reports the electrical characteristics of La-Sc oxides complex and effect of nitrogen incorporation for applications to high-k gate stack. We found that V_fb can be controlled by the ScO concentration. Moreover, large bumps in C-V curves, which indicate high interfacial state density, can be suppressed with large ScO concentration. nMOSFETs using the La-Sc oxides complex in the gate stack are fabricated. In addition, nitrogen incorporation into the La-Sc oxide films was fond to be useful to suppress the EOT growth during annealing at high temperatures.     

Reliability of HTO based high-voltage gate stacks for flash memories

We report on the excellent reliability performance of high-voltage (HV) gate stacks comprised of a thin thermal oxide and a thicker HTO layer. Time-to-breakdown of the developed stacks exceeded corresponding values for thermal HV oxides of the same thickness. Peculiarities of current relaxation in course of electrical stress tests are interpreted by injected charge trapping in HTO and new trap generation. Charge trapping in optimized HTO is low and guarantees reliable device operation.     

Electrical characterization of polymer-based FETs fabricated by spin-coating poly(3-alkylthiophene)s

The current-voltage (I-V) characteristics of two different polymer thin-film transistors (TFTs), based on spin-coating of poly(3-hexylthiophene)-P3HT and poly(3-hexadecylthiophene)-P3HDT, are studied. A model is developed to interpret the results and to explain the differences between these two polymers. Various parameters of the semiconducting polymers, including bulk mobility, field-effect mobility, trap density, and unintentional dopant concentration are estimated. The model takes into account the domination of the bulk current over the channel current in the subthreshold regime as well as the effects of the depletion layer as parasitic resistances in series with the channel resistance. Furthermore, the effects of the films thickness on the electrical characteristics of these TFTs are discussed. Compared to the P3HT, the P3HDT-based TFT has a lower subthreshold slope, higher on current ratio, and higher field-effect mobility.     

A new refractory self-aligned gate technology for GaAs microwavepower FETs and MMICs

The authors fabricated GaAs power FETs and microwave ICs using a novel fully planar, refractory self-aligned gate process. This process uses methods to reduce the gate resistance and output conductance without sacrificing simplicity. Because it is compatible with the use of an optical stepper, the process is suitable for manufacturing use. The C-band RF performance is excellent; the very uniform and reproducible device parameters resulted in a first-iteration 2.5-W C -band power amplifier that met design specifications on the first lot of wafers processed     

A novel model of the gate current in heterojunction FETs

The authors present a model of the gate current in heterojunction FETs that takes into account two-dimensional electron gas effects at the heterojunction interface. The gate current results from tunnel and thermionic contributions. This model takes into account a number of technological parameters such as heterojunction barrier height, threshold voltage, gate length, and temperature. It has been tested against experimental measurements of gate current in AlGaAs/GaAs MISFETs at various temperatures. The agreement has been found quite satisfactory in a large range of temperatures     

Modeling of direct tunneling current through gate dielectric stacks

The direct tunneling current has been calculated for the first time from an inverted p-substrate through different gate dielectrics by numerically solving Schroedinger's equation and allowing for wavefunction penetration into the gate dielectric stack. The numerical solution adopts a first-order perturbation approach to calculate the lifetime of the quasi-bound states. This approach has been verified to be valid even for extremely thin dielectrics (0.5 nm). The tunneling currents predicted by this technique compare well with the WKB solution. Also for the first time investigation of the wavefunction penetration into gate stacks and their effects on quantization in the substrate has also been performed. For the same effective oxide thickness (EOT) the direct tunneling current decreases with increasing dielectric constant, as expected. However, in order to take full advantage of using high-K dielectrics as gate insulators the interfacial oxide needs to be eliminated     

Application of combinatorial methodologies for work function engineering of metal gate/high-κ advanced gate stacks

This paper uses combinatorial methodologies to investigate the effect of TaN-AlN metal gate electrode composition on the work function, for (TaN-AlN)/Hf-Si-O/SiO₂/Si capacitors. We demonstrate the efficacy of the combinatorial technique by plotting work function for more than thirty Ta_1-xAl_xN_y compositions, with x varying from 0.05 to 0.50. The work function is shown to continuously decrease, from about 4.9 to about 4.7 eV, over this range. Over the same range, oxide fixed charge is seen to go from about -2.5 × 10¹² cm⁻³ to about zero. The work functions reported here are about 0.1 eV higher than in a previous study, but are still about 0.2 eV smaller than required for PMOS device applications.     

Electrical properties of Ru-based alloy gate electrodes for dualmetal gate Si-CMOS

In this letter, low resistivity Ru and Ru-Ta alloy films, deposited via reactive sputtering, were evaluated as gate electrodes for p- and n-MOSFET devices, respectively. MOSFETs fabricated via a conventional process flow indicated that the work functions of Ru and Ru-Ta alloys were compatible with p- and n-MOSFET devices, respectively. Both of the metal gated devices eliminated gate depletion effects. Good MOSFET characteristics, such as I_DS-V_GS and mobility, were obtained for both Ru-gated PMOSFETs and Ru-Ta gated NMOSFETs     

Effect of polysilicon gate type on the flatband voltage shift forultrathin oxide-nitride gate stacks

In this work, we demonstrate that the magnitude of flatband voltage (V_FB) shift for ultrathin (<2 nm) silicon dioxide-silicon nitride (ON) gate stacks in MOSFET's depends on the Fermi level position in the gate material. In addition, a fixed positive charge at the oxide-nitride interface was observed     

Influence of gate intervals on the behaviour of submicron dual-gate FETs

A simple, self-consistent model, taking into account the non-stationary electron dynamic effects, is used to study the behaviour of submicron dual-gate FETs. It shows that the conventional model, based on the connection of two field-effect transistors in cascade, is no longer valid when the intergate distances become smaller than 0.6 ?m.     

Investigation and statistical modeling of InAs-based double gate tunnel FETs for RF performance enhancement

In this paper,RF performance analysis of InAs-based double gate (DG) tunnel field effect transistors (TFETs) is investigated in both qualitative and quantitative fashion.This investigation is carried out by varying the geometrical and doping parameters of TFETs to extract various RF parameters,unity gain cut-off frequency (ft),maximum oscillation frequency (fmax),intrinsic gain and admittance (Y) parameters.An asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs.Higher ON-current (ION) of about 0.2 mA and less leakage current (IOFF) of 29 fA is achieved for DG TFET with gate-drain overlap.Due to increase in transconductance (gm),higherf and intrinsic gain is attained for DG TFET with gate-drain overlap.Higher fmax of 985 GHz is obtained for drain doping of 5 × 1017 cm-3 because of the reduced gate-drain capacitance (Cgd) with DG TFET with gate-drain overlap.In terms of Y-parameters,gate oxide thickness variation offers better performance due to the reduced values of Cgd.A second order numerical polynomial model is generated for all the RF responses as a function of geometrical and doping parameters.The simulation results are compared with this numerical model where the predicted values match with the simulated values.     

Density functional theory of high-k dielectric gate stacks

Density functional theory is the method of choice in theoretical materials science. It has also proved to be a useful tool in device engineering, particularly at nanoscale and when novel materials are involved. In this paper, we briefly review recent theoretical results in the area of the advanced gate stack materials engineering.     

An improved model for noise characterization of microwave GaAs FETs

A broadband noise model for microwave FETs has been described. The model consists of small-signal lumped elements together with two noise sources. A measurement of broadband S parameters plus a single-frequency measurement of optimum source susceptance can yield enough information to determine the model, although greater accuracy is obtained using additional noise data to determine the precise value of the gate resistance. The model's predictions match well with measured noise parameter data for a high-performance GaAs FET over a wide frequency range     

Interfacial layer optimization of high-k/metal gate stacks for low temperature processing

Understanding the requirements for obtaining high mobility gate stacks in a low temperature process is crucial for enabling a low temperature integration flow. A low temperature integration scheme may be necessary for higher-k dielectrics (k > 25) or for extremely scaled devices (<15 nm node). This paper demonstrates that nitrogen free interfaces are required for high mobility gate stacks in a low temperature (600 °C) process flow.     

异质栅氧化层轻掺杂漏石墨烯纳米条带p-i-n隧穿场效应管量子输运特性的研究

We perform a theoretical study of the effects of the lightly doped drain （LDD） and high-k dielectric on the performances of double gate p-i-n tunneling graphene nanoribbon field effect transistors （TFETs）. The models are based on non-equilibrium Green＇s functions （NEGF） solved self-consistently with 3D-Poisson＇s equations. For the first time, hetero gate dielectric and single LDD TFETs （SL-HTFETs） are proposed and investigated. Simulation results show SL-HTFETs can effectively decrease leakage current, sub-threshold swing, and increase on-off current ratio compared to conventional TFETs and Si-based devices; the SL-HTFETs from the 3p ＋ 1 family have better switching characteristics than those from the 3p family due to smaller effective masses of the former. In addition, comparison of scaled performances between SL-HTFETs and conventional TFETs show that SL-HTFETs have better scaling properties than the conventional TFETs, and thus could be promising devices for logic and ultra-low power applications.     

Power gain and noise of InP and GaAs insulated gate microwave FETs

LPE GaAs and InP n-channel depletion mode insulated gate field effect transistors (MISFETs) having 4 μm gate lengths have been fabricated employing pyrolytic Si_xO_yN_z, pyrolytic SiO₂ and an anodic dielectric for gate insulation.The microwave power gain, noise figure, maximum output power and power-added efficiency were measured and compared to those parameters measured on GaAs Schottky barrier gate devices of identical geometry. The results show that, at least at the microwave frequencies measured, power gain and noise are essentially the same in the GaAs Schottky gate FET and anodic MISFET devices while the maximum output power of a typical InP MISFET was greater than that of a representative GaAs Schottky device.     

Improved analytical model of surface potential with modified boundary conditions for double gate tunnel FETs

In this paper, an improved analytical model of the channel surface potential in the tunnel field effect transistors is established with modified boundary conditions considering the source and drain depletion widths, avoiding the deviation of the channel potential and the overestimate on the electric field. Based on the proposed surface potential model, the threshold voltage model is also developed with the transconductance change method. The influences of the channel and oxide structures on surface potential and threshold voltage are investigated. The good agreement is obtained by the comparison of the modeling results with the numerical simulation results, verifying the validation of the proposed model, and it also implied that this model will be helpful for the further investigation of TFETs.