The determination of the interface-state density distribution from the capacitance-frequency measurements in Au/n-Si schottky barrier diodes

The Au/n-Si Schottky barrier diodes (SBDs) with 200-μm (sample D200) and 400-μm (sample D400) bulk thicknesses have been fabricated. The ideality factor and the barrier height have been calculated from the forward-bias current-voltage (I-V) characteristics of D200 and D400 SBDs. The energy distribution of the interface states and relaxation time are found from the capacitance-frequency (C-f) characteristics. The density of interface state and relaxation times have a (nearly constant) slow exponential rise with bias in the range of E_c −0.77 and E_c −0.47 eV from the midgap toward the bottom of the conductance band. Furthermore, the energy distribution of the interface states obtained from C-f characteristics has been compared with that obtained from the forward-bias I-V characteristics.     

Current transport mechanisms and deep level transient spectroscopy of Au/n-Si Schottky barrier diodes

The temperature-dependent electrical characteristics of the Au/n-Si Schottky diodes have been studied in the temperature range of 40-300 K. Current density-voltage (J-V) characteristics of these diodes have been analyzed on the basis of thermionic emission theory with Gaussian distribution model of barrier height. The basic diode parameters such as rectification ratio, ideality factor and barrier height were extracted. Under a reverse bias, the conduction process at low voltage is determined by Schottky emission over a potential barrier but at higher voltage the Poole Frenkel effect is observed. The capacitance-voltage (C-V) features of the Au/n-Si Schottky diodes were characterized in the high frequency of 1 MHz. The barrier heights values obtained from the J-V and C-V characteristics have been compared. It has been seen that the barrier height value obtained from the C-V measurements is higher than that obtained from the J-V measurements at various temperatures. Possible explanations for this discrepancy are presented. Deep level transient spectroscopy (DLTS) has been used to investigate deep levels in Au/n-Si. Three electron trap centers, having different emission rates and activation energies, have been observed. It is argued that the origin of these defects is of intrinsic nature. A correlation between C-V and DLTS measurements is investigated.     

The analysis of the electrical characteristics and interface state densities of Re/n-type Si Schottky barrier diodes at room temperature

The main electrical characteristics of current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature of the Re/n-type Si Schottky barrier diodes prepared by pulsed laser deposition (PLD) method have been examined. The values of the basic electrical properties such as forward saturation current (I_o), ideality factors (n), barrier heights (Ф_bo), rectification ratio (RR) and series resistances (R_S) were obtained from I-V and C-V measurements using different calculation methods. At low voltages (V ≤ 0.3 V), the electrical conduction was formed to take place by thermionic emission, whereas at high voltages (V > 0.3 V), a space charge limited conduction mechanism was shown. Furthermore, the interface state densities (N_SS) as a function of energy distribution (E_SS- E_V) was obtained from the I-V data by taking into account the bias dependence of the effective barrier height (Φ_b) for the Re/n-type Si Schottky barrier diodes.     

Electrical and interfacial properties of Au/P3HT:PCBM/n-Si Schottky barrier diodes at room temperature

In this study, a gold/poly(3-hexylthiophene):[6,6]-phenyl C61 butyric acid methyl ester/n-type silicon (Au/P3HT:PCBM/n-Si) metal-polymer-semiconductor (MPS) Schottky barrier diode (SBD) was fabricated. To accomplish this, a spin-coating system and a thermal evaporation were used for preparation of a P3HT/PCBM layer system and for deposition of metal contacts, respectively. The forward- and reverse-bias current–voltage (I–V) characteristics of the MPS SBD at room temperature were studied to investigate its main electrical parameters such as ideality factor (n), barrier height (Φ_B), series resistance (R_s), shunt resistance (R_sh), and density of interface states (N_ss). The I–V characteristics have nonlinear behavior due to the effect of R_s, resulting in an n value (3.09) larger than unity. Additionally, it was found that n, Φ_B, R_s, R_sh, and N_ss have strong correlation with the applied bias. All results suggest that the P3HT/PCBM interfacial organic layer affects the Au/P3HT:PCBM/n-Si MPS SBD, and that R_s and N_ss are the main electrical parameters that affect the Au/P3HT:PCBM/n-Si MPS SBD. Furthermore, a lower N_ss compared with that of other types of MPS SBDs in the literature was achieved by using the P3HT/PCBM layer. This lowering shows that high-quality electronic and optoelectronic devices may be fabricated by using the Au/P3HT:PCBM/n-Si MPS SBD.     

Frequency and voltage dependence of admittance characteristics of Al/Al2O3/PVA:n-ZnSe Schottky barrier diodes

This paper reports the frequency dependence of admittance measurements i.e C–V and G/ω–V characteristics of Al/Al₂O₃/PVA:n-ZnSe MIS diode. The interface states (N_ss) and series resistance (R_s) of the MIS diode strongly influence the C–V–f and G/ω–V–f characteristics. The conductance method is used to calculate the series resistance (R_s), the density of states (N_ss), insulator layer capacitance and thickness. The frequency dependent dieclectric parameters such as dielectric constant (εʹ), dielectric loss (ε″), loss tangent (tan δ) and a.c. electrical conductivity (σ_ac) has been calculated and which are also responsible for observed frequency dispersion in C–V and G/ω curves.     

Effects of PCBM concentration on the electrical properties of the Au/P3HT:PCBM/n-Si (MPS) Schottky barrier diodes

In this study, the gold/poly(3-hexylthiophene):[6,6]-phenyl C61 butyric acid methyl ester/n-type silicon (Au/P3HT:PCBM/n-Si) metal–polymer–semiconductor (MPS) Schottky barrier diodes (SBDs) were investigated in terms of the effects of PCBM concentration on the electrical parameters. The forward and reverse bias current–voltage (I–V) characteristics of the Au/P3HT:PCBM/n-Si MPS SBDs fabricated by using the different P3HT:PCBM mass ratios were studied in the dark, at room temperature. The main electrical parameters, such as ideality factor (n), barrier height (Φ_B0), series resistance (R_s), shunt resistance (R_sh), and density of interface states (N_ss) were determined from I–V characteristics for the different P3HT:PCBM mass ratios (2:1, 6:1 and 10:1) used diodes. The values of n, R_s, Φ_B0, and N_ss were reduced, while the carrier mobility and current were increased, by increasing the PCBM concentration in the P3HT:PCBM organic blend layer. The ideal values of electrical parameters were obtained for 2:1 P3HT:PCBM mass ratio used diode. This shows that the electrical properties of MPS diodes strongly depend on the PCBM concentration of the P3HT:PCBM organic layer. Moreover, increasing the PCBM concentration in P3HT:PCBM organic blend layer improves the quality of the Au/P3HT:PCBM/n-Si (MPS) SBDs which enables the fabrication of high-quality electronic and optoelectronic devices.     

Annealing temperature effect on electrical and structural properties of Cu/Au Schottky contacts to n-type GaN

Schottky contacts were fabricated on n-type GaN using a Cu/Au metallization scheme, and the electrical and structural properties have been investigated as a function of annealing temperature by current-voltage (I-V), capacitance-voltage (C-V), Auger electron spectroscopy (AES) and X-ray diffraction (XRD) measurements. The extracted Schottky barrier height of the as-deposited contact was found to be 0.69 eV (I-V) and 0.77 eV (C-V), respectively. However, the Schottky barrier height of the Cu/Au contact slightly increases to 0.77 eV (I-V) and 1.18 eV (C-V) when the contact was annealed at 300 °C for 1 min. It is shown that the Schottky barrier height decreases to 0.73 eV (I-V) and 0.99 eV (C-V), 0.56 eV (I-V) and 0.87 eV (C-V) after annealing at 400 °C and 500 °C for 1 min in N₂ atmosphere. Norde method was also used to extract the barrier height of Cu/Au contacts and the values are 0.69 eV for the as-deposited, 0.76 eV at 300 °C, 0.71 eV at 400 °C and 0.56 eV at 500 °C which are in good agreement with those obtained by the I-V method. Based on Auger electron spectroscopy and X-ray diffraction results, the formation of nitride phases at the Cu/Au/n-GaN interface could be the reason for the degradation of Schottky barrier height upon annealing at 500 °C.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

Frequency and voltage effects on the dielectric properties and electrical conductivity of Al-TiW-Pd2Si/n-Si structures

Different from conventional metal-Si compounds-n-Si structures, the thin film of TiW alloy was deposited on Pd₂Si-n-Si to form a diffusion barrier between aluminum (Al) and Pd₂Si-n-Si. Dielectric properties and electrical conductivity of TiW-Pd₂Si/n-Si structures in the frequency range of 5 kHz-10 MHz and voltage range of (−4 V) to (10 V) have been investigated in detail by using experimental C-V and G-V measurements. Experimental results indicate that the values of ε′ show a steep decrease with increasing frequency for each voltage. On the other hand, the values of ε″ show a peak, and its intensity increases with decreasing voltage and shifts towards the lower frequency side. The ac electrical conductivity (σ_ac) and the real part of electric modulus (M′) increase with increasing frequency. Also, the imaginary part of electric modulus (M″) shows a peak and the peak position shifts to higher frequency with increasing applied voltage. It can be concluded that the interfacial polarization can be more easily occurred at low frequencies, and the majority of interface states at metal semiconductor interface, consequently contributes to deviation of dielectric properties of TiW-Pd₂Si/n-Si structures.     

The profile of temperature and voltage dependent series resistance and the interface states in (Ni/Au)/Al0.3Ga0.7N/AlN/GaN heterostructures

The temperature dependence of capacitance-voltage (C-V) and the conductance-voltage (G/w-V) characteristics of (Ni/Au)/Al_0.3Ga_0.7N/AlN/GaN heterostructures were investigated by considering the effect of series resistance (R_s) and interface states N_ss in a wide temperature range (79-395 K). Our experimental results show that both R_s and N_ss were found to be strongly functional with temperature and bias voltage. Therefore, they affect the (C-V) and (G/w-V) characteristics. The values of capacitance give two peaks at high temperatures, and a crossing at a certain bias voltage point (∼3.5 V). The first capacitance peaks are located in the forward bias region (∼0.1 V) at a low temperature. However, from 295 K the second capacitance peaks appear and then shift towards the reverse bias region that is located at ∼−4.5 V with increasing temperature. Such behavior, as demonstrated by these anomalous peaks, can be attributed to the thermal restructuring and reordering of the interface states. The capacitance (C_m) and conductance (G/w-V) values that were measured under both reverse and forward bias were corrected for the effect of series resistance in order to obtain the real diode capacitance and conductance. The density of N_ss, depending on the temperature, was determined from the (C-V) and (G/w-V) data using the Hill-Coleman Method.     

On the temperature dependence of series resistance and interface states in Al/SiO2/p-Si (MIS) Schottky diodes

The capacitance-voltage-temperature (C-V-T) and conductance-voltage-temperature (G/w-V-T) characteristics of metal-semiconductor (Al/p-Si) Schottky diodes with thermal growth interfacial layer were investigated by considering series resistance effect in the wide temperature range (80-400 K). It is found that in the presence of series resistance, the forward bias C-V plots exhibit a peak, and experimentally shows that the peak positions shift towards higher positive voltages with increasing temperature, and the peak value of the capacitance has a maximum at 80 K. The C-V and (G/w-V) characteristics confirm that the N_ss and R_s of the diode are important parameters that strongly influence the electric parameters in (Al/SiO₂/p-Si) MIS Schottky diodes. The crossing of the G/w-V curves appears as an abnormality when seen with respect to the conventional behaviour of the ideal MS or MIS Schottky diode. It is thought that the presence of a series resistance keeps this intersection hidden and unobservable in homogeneous Schottky diodes, but it appears in the case of inhomogeneous Schottky diode. In addition, the high frequency (C_m) and conductance (G_m/w) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance.