自适应计算提高了IC的性能

硅CMOS器件的一种新颖的结构,既提高了性能,又降低了功耗,并且还缩小了芯片的面积     

FPGA设计中功耗的分析与仿真

FPGA的应用越来越广泛,随着制造工艺水平的不断提升,越来越高的器件密度以及性能使得功耗因数在FPGA设计中越来越重要。器件中元件模块的种类和数量对FPGA设计中功耗的动态范围影响较大,对FPGA的电源功耗进行了分析,并介绍了如何利用Altera公司的PowerPlay Early Power Estimator这一工具在设计前期尽可能准确地估计功耗并通过估计功耗对硬件设计进行优化选择。     

按比例缩小技术在微纳米中的挑战和对策

按比例缩小技术是驱动集成电路发展的一项关键技术 ,在进入微纳米后出现了一系列的挑战。文中分析了按比例缩小在光刻技术、器件的亚阈特性、互连延迟以及功耗等方面面临的一些问题 ,同时从工艺、器件、电路、设计等方面提出一些相应的解决方法     

AnalogicTech公司LDO线性稳压器

Advanced Analogic Technologies公司推出一款具有微功耗重置功能的LDO线性调节器AAT3258。该器件把300mA LDO调节器和低电流微处理器重置电路结合起来，空间仅为两个单独器件的一半，缩小了手持设备如手机、PDA、数码相机和笔记本电脑的板尺寸。AAT3258适用于快速起动和快速关断时序，     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

Ultra-Thin Body SOI MOSFET交流特性分析和结构优化

针对沟道长度为50nm的UTB SOI器件进行了交流模拟工作，利用器件主要的性能参数，详细分析了UTB结构的交流特性．通过分析UTB SOI器件的硅膜厚度、侧墙宽度等结构参数对器件交流特性的影响，对器件结构进行了优化．最终针对UTB SOI MOSFET结构提出了一种缓解速度和功耗特性优化之间矛盾的方法，从而实现了结构参数的优化选取，使UTB SOI MOSFET器件的应用空间更为广泛．     

一种性能优良稳定的微功耗CMOS电压积分器

本文提出了一种电源波动影响弱、低温飘、微功耗（〈1μw）的CMOS电压型积分器电路。它利用自偏置的恒流源电路结构以及MOSFETs的亚阈值特性产生一个nA级的恒流源，通过控制电路实现对电容充放电来获得积分电压。并且对电路结构、器件类型和器件尺寸进行了优化。仿真结果表明，得到了独立于电源电压、低温度系数、微功耗的积分电压。     

MOSFET亚阈特性分析与低温按比例缩小理论的研究

器件尺寸按比例缩小是实现超大规模集成电路的有效途径，但寄生和二级效应却将器件限在一定的水平，本文在对比分析常温与低温下小尺寸器件效应的基础上，重点研究了ＭＯＳ器件亚阈特性对器件性能及按比例缩小的影响，并根据低温工作的特点，提出了ＭＯＳ器件一种低温按比例缩小规则，该原则对低温器的优化设计，从而更大程度在提高电路与系统性能具有重要的指导意义。     

大功率IGBT功耗的研究

绝缘栅双极晶体管(IGBT)是复合全控型电压驱动式功率半导体器件.为了改善其功耗性能并进行进一步优化,论文在阐述IGBT特性基础上,通过从器件构成和实际应用角度对影响功率器件功耗的主要因素进行分析,并结合实践对IGBT功率器件的功耗进行深入研究,由此可以更深刻地理解IGBT功耗的产生,这对正确选择和使用IGBT器件及其系统有一定的实用价值.     

锗硅选择性外延在应变技术中的应用

多年以来,沿着摩尔定律的途径,人们一直采用对金属氧化物半导体场效应晶体管（MOSFET）进行等比例微缩来增加器件速度的方法。然而在晶体管尺寸达到65nm以后，常规的微缩方法遇到了以短沟道效应为核心的一系列问题。当器件进一步微缩，随着电流密度的增大，迁移率的提升成为保持晶体管性能的关键．因为电源电压被等比例缩小以降低芯片的动态功耗。     

Process evaluation in FinFET based 7T SRAM cell

Analog Integrated Circuits and Signal Processing - The main aim of device scaling or usage of different technology is to reduce power. The major problem with technology scaling is power dissipation...     

Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-/spl mu/m CMOS

The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain reliability. These continual scaling requirements on supply and threshold voltages pose several technology and circuit design challenges. With threshold voltage scaling, subthreshold leakage power is expected to become a significant portion of the total power in future CMOS systems. Therefore, it becomes crucial to predict and reduce subthreshold leakage power of such systems. In the first part of this paper, we present a subthreshold leakage power prediction model that takes into account within-die threshold voltage variation. Statistical measurements of 32-bit microprocessors in 0.18-/spl mu/m CMOS confirm that the mean error of the model is 4%. In the second part of this paper, we present the use of stacked devices to reduce system subthreshold leakage power without reducing system performance. A model to predict the scaling nature of this stack effect and verification of the model through statistical device measurements in 0.18-/spl mu/m and 0.13-/spl mu/m are presented. Measurements also demonstrate reduction in threshold voltage variation for stacked devices compared to nonstack devices. Comparison of the stack effect to the use of high threshold voltage or longer channel length devices for subthreshold leakage reduction is also discussed.     

The impact of device scaling and power supply change on CMOS gateperformance

Based a new empirical mobility model that is solely dependent on V _gs, V_t, and T_ox and a corresponding saturation drain current (I_dsat) model, the impact of device scaling and power supply voltage change on CMOS inverter's performance is investigated in this paper. It shows that the T_ox which maximizes inverter's speed may be thicker than reliability consideration requires. In addition, very high speed can be achieved even at low V_dd (for low power applications) if V_t can be lowered     

Device optimization for digital subthreshold logic operation

Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) can have orders of magnitude power advantage over standard CMOS circuits for applications requiring ultralow power and medium frequency of operation. Although the implication of technology scaling on subthreshold operation is not obvious (since an obsolete technology node can deliver the same performance as a scaled technology in subthreshold), it has been shown that technology scaling helps to reduce the supply-voltage and, hence, the power consumption at iso-performance. It is possible to implement subthreshold logic circuits using the standard transistors that are designed primarily for ultra high performance super-threshold logic design. However, an Si MOSFET so optimized for performance in the super-threshold regime is not the best device to use in the subthreshold domain. We propose device designs apt for subthreshold operation. Results show that the optimized device improves the delay and power delay product (PDP) of an inverter chain by 44% and 51%, respectively, over the normal super-threshold device operated in the subthreshold region.     

Experimental study of AlGaAs/GaAs HBT device design for powerapplications

An experimental study of AlGaAs/GaAs heterojunction bipolar transistor (HBT) device design for optimizing key DC and RF performance parameters relevant to power device applications is reported. The design of the collector, base, and base-emitter junction is investigated for improved power device performance, and novel device structures are presented. Device scaling effects and the extent to which air-bridged interconnect can reduce parasitics in large power devices are also explored. Power HBTs employing some of the optimized design features have achieved a power output of 1.2 W (4 W/mm) with 43% power-added efficiency at 10 GHz     

Nanometer Device Scaling in Subthreshold Logic and SRAM

Subthreshold circuit design is promising for future ultralow-energy sensor applications as well as highly parallel high-performance processing. Device scaling has the potential to increase speed in addition to decreasing both energy and cost in subthreshold circuits. However, no study has yet considered whether device scaling to 45 nm and beyond will be beneficial for subthreshold logic. We investigate the implications of device scaling on subthreshold logic and SRAM and And that the slow scaling of gate-oxide thickness leads to a 60% reduction in I_on/I_off between the 90- and 32-nm device generations. We highlight the effects of this device degradation on noise margins, delay, and energy. We subsequently propose an alternative scaling strategy and demonstrate significant improvements in noise margins, delay, and energy in sub-V_th circuits. Using both optimized and unoptimized subthreshold device models, we explore the robustness of scaled subthreshold SRAM. We use a simple variability model and find that even small memories become unstable at advanced technology nodes. However, the simple device optimizations suggested in this paper can be used to improve nominal read noise margins by 64% at the 32-nm node.     

An analytical model for predicting the remaining battery capacity of lithium-ion batteries

Predicting the residual energy of the battery source that powers a portable electronic device is imperative in designing and applying an effective dynamic power management policy for the device. This paper starts up by showing that a 30% error in predicting the battery capacity of a lithium-ion battery can result in up to 20% performance degradation for a dynamic voltage and frequency scaling algorithm. Next, this paper presents a closed form analytical expression for predicting the remaining capacity of a lithium-ion battery. The proposed high-level model, which relies on online current and voltage measurements, correctly accounts for the temperature and cycle aging effects. The accuracy of the high-level model is validated by comparing it with DUALFOIL simulation results, demonstrating a maximum of 5% error between simulated and predicted data.     

Power consumption of analog circuits: a tutorial

A systematic approach to the power consumption of analog circuits is presented. The power consumption is related to basic circuit requirements, as dynamic range, bandwidth, noise figure and sampling speed and is considering basic device and device scaling behavior. Several kinds of circuits are treated, as samplers, amplifiers, filters and oscillators. The objective is to derive lower bounds to power consumption in analog circuits, to be used as design targets when designing power-constrained analog systems.     

辐射效应对半导体器件的影响及加固技术

与其他半导体器件相比,CMOS集成电路具有功耗小、噪声容限大等优点,对于对重量、体积、能源消耗都有严格要求的卫星和宇宙飞船来说,CMOS集成电路是优先选择的器件种类。随着半导体器件的等比例缩小,辐射效应对器件的影响也在跟着变化。这些影响包括:栅氧化层厚度、栅长的减小、横向非均匀损伤、栅感应漏电流等方面。对于微电子器件的抗辐射加固,文章就微电子器件的应用场合、辐射环境的辐射因素和强度等,从微电子器件的制作材料、电路设计、器件结构、工艺等多方面进行加固考虑,针对各种应用环境提出加固方案。