Impact of single pMOSFET dielectric degradation on NAND circuit performance

Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source-to-drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.     

Negative bias temperature instability mechanisms in p-channel power VDMOSFETs

The negative bias temperature stress induced instabilities of threshold voltage in commercial p-channel power VDMOSFETs have been investigated. The threshold voltage shifts, which are more pronounced at higher voltages and/or temperatures, are caused by the NBT stress induced buildup of both oxide trapped charge and interface traps. However, the observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge. The results are analysed in terms of the mechanisms responsible for buildup of oxide charge and interface traps, and the model that explains experimental data is discussed in details.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability

A paradigm for MOSFET instabilities is outlined based on gate oxide traps and the detailed understanding of their properties. A model with trap energy levels in the gate dielectric and their misalignment with the channel Fermi level is described, offering the most successful strategy to reduce both Positive and Negative Bias Temperature Instability (PBTI and NBTI) in a range of gate stacks. Trap temporal properties are determined by tunneling between the carrier reservoir and the trap itself, as well as thermal barriers related to atomic reconfiguration. Trap electrostatic impact depends on the gate voltage and its spatial position, randomized by variations in the channel potential. All internal properties of traps are distributed, resulting in distributions of the externally observable trap parameters, and in turn in time-dependent variability in devices and circuits.     

Pocket implantation effect on drain current flicker noise in analog nMOSFET devices

The pocket implantation effect on drain current flicker noise in 0.13 /spl mu/m CMOS process based high performance analog nMOSFETs is investigated. Our result shows that pocket implantation will significantly degrade device low-frequency noise primarily because of nonuniform threshold voltage distribution along the channel. An analytical flicker noise model to account for a pocket doping effect is proposed. In our model, the local threshold voltage and the width of the pocket implant region are extracted from the measured reverse short-channel effect, and the oxide trap density is extracted from a long-channel device. Good agreement between our model and the measurement result is obtained without other fitting parameters.     

A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient

A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large- and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.     

Analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions

Physics-based analytical threshold voltage model for cylindrical surrounding-gate MOSFET with electrically induced source/drain extensions is presented. The effect of inversion carriers on the channel’s potential is considered in presented model. Using this analytical model, the characteristics of EJ-CSG are investigated in terms of surface potential and electric field distribution, threshold voltage roll-off, and DIBL. Results show that the application of electrically induced S/D extensions to the cylindrical surrounding-gate MOSFET will successfully suppress the hot-carrier effects, threshold voltage roll-off, and DIBL. It is also revealed that a moderate side-gate bias voltage, a small gate oxide thickness, and a small silicon channel radius are needed to improve device characteristics. The derived analytical model is verified by its good agreement with the three-dimensional numerical device simulator ISE.     

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps and H⁺ ions are proposed to be responsible for interface trap buildup.     

热载流子应力下n-MOSFET线性漏电流的退化

研究了不同沟道和栅氧化层厚度的n-M O S器件在衬底正偏压的VG=VD/2热载流子应力下,由于衬底正偏压的不同对器件线性漏电流退化的影响。实验发现衬底正偏压对沟长0.135μm,栅氧化层厚度2.5 nm器件的线性漏电流退化的影响比沟长0.25μm,栅氧化层厚度5 nm器件更强。分析结果表明,随着器件沟长继续缩短和栅氧化层减薄,由于衬底正偏置导致的阈值电压减小、增强的寄生NPN晶体管效应、沟道热电子与碰撞电离空穴复合所产生的高能光子以及热电子直接隧穿超薄栅氧化层产生的高能光子可能打断S i-S iO2界面的弱键产生界面陷阱,加速n-M O S器件线性漏电流的退化。     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Statistical static timing analysis for circuit aging prediction

Complementary metal oxide semiconductor ( CMOS) aging mechanisms including bias temperature instability ( BTI) pose growing concerns about circuit reliability. BTI results in threshold voltage increases on CMOS transistors, causing delay shifts and timing violations on logic circuits. The amount of degradation is dependent on the circuit workload, which increases the challenge for accurate BTI aging prediction at the design time. In this paper, a BTI prediction method for logic circuits based on statistical static timing analysis (SSTA) is proposed, especially considering the correlation between circuit workload and BTI degradation. It consists of a training phase, to discover the relationship between circuit scale and the required workload samples, and a prediction phase, to present the degradations under different workloads in Gaussian probability distributions. This method can predict the distribution of degradations with negligible errors, and identify 50% more BTI-critical paths in an affordable time, compared with conventional methods.     

Correlation of stress-induced leakage current in thin oxides withtrap generation inside the oxides

Increases in pre-tunneling leakage currents in thin oxides after the oxides are subjected to high voltage stresses are correlated with the number of traps generated inside of the oxides by the high-voltage stresses. The densities of the traps are calculated using the tunneling front model and analyzing the transient currents that flowed through the oxide after removal of the stress voltage pulses. It is found that the trap distributions are relatively uniform throughout the small portion of the oxide sampled by the transient currents. The trap densities increase as the cube root of the fluence of electrons that passes through the oxide during the stress, independent of the stress polarity. The voltage dependence of the low-level pretunneling current is dependent on the sequence in which the stress voltage polarities and the low-level current measurement polarities are applied. The portion of the low-level pre-tunneling current that is not dependent on the polarity sequence is best fitted by a voltage dependence consistent with Schottky emission     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

The relaxation phenomena of positive charges in thin gate oxideduring Fowler-Nordheim tunneling stress

In this study, new relaxation phenomena of positive charges in gate oxide with Fowler-Nordheim (FN) constant current injections have been investigated and characterized. It was found that the magnitudes of applied gate voltage shifts (ΔV_FN) during FN injections, after positive charges relaxed or discharged, have a logarithmic dependence with the relaxation time for both injection polarities. The results can derive the relationship of transient discharging currents, that flow through the oxides after removal of the stress voltage, with the relaxation time. We have shown that the current has a 1/f dependence for both injection polarities which can be also derived from the tunneling front model. The effects of oxide fields (lower than the necessary voltage for FN tunneling) and wafer temperatures (373 and 423 K) for the relaxation of positive charges are also studied     

Mechanism of Dynamic Bias Temperature Instability in p- and nMOSFETs: The Effect of Pulse Waveform

The waveform effect on dynamic bias temperature instability (BTI) is systematically studied for both p- and nMOSFETs with ultrathin SiON gate dielectrics by using a modified direct-current current–voltage method to monitor the stress-induced interface trap density. Interface traps are generated at the inversion gate bias (negative for pMOSFETs and positive for nMOSFETs) and are partially recovered at the zero or accumulation gate bias. Devices under high-frequency bipolar stress exhibit a significant frequency-dependent degradation enhancement. Approximate analytical expressions of the interface trap generation for devices under the static, unipolar, or bipolar stress are derived in the framework of conventional reaction–diffusion (R–D) model and with an assumption that additional interface traps$(N_ it^ast)$are generated in each cycle of the dynamic stress. The additional interface trap generation is proposed to originate from the transient trapped carriers in the states at and/or near the$hboxSiO_2/hboxSi$interface upon the gate voltage reversal from the accumulation bias to the inversion bias quickly, which may accelerate dissociation of Si–H bonds at the beginning of the stressing phase in each cycle. Hence,$N_ it^ast$depends on the interface-state density, the voltage at the relaxation (i.e., accumulation) bias, and the transition time of the stress waveform (the fall time for pMOSFETs and the rise time for nMOSFETs). The observed dynamic BTI behaviors can be perfectly explained by this modified R–D model.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.     

Nonvolatile analog memory in MNOS capacitors

Long-term storage of analog signals of wide dynamic range has been successfully demonstrated for the first time in single MNOS capacitors. After a reset state is established by majority carrier tunneling, measured pulses of light are used to generate minority carriers which tunnel to nitride traps and in turn induce shifts in the flat-band voltage proportional to the minority carrier charge. Linear voltage windows of 12 volts are observed, and logarithmic decay rates are as low as 30 mV per decade of storage time per volt of initial flat-band shift. Analog signals can be stored linearly over a dynamic range of 40 dB for 30 hours.     

Investigation of oxide charge trapping and detrapping in a MOSFETby using a GIDL current technique

We proposed a new measurement technique to investigate oxide charge trapping and detrapping in a hot carrier stressed n-MOSFET by measuring a GIDL current transient. This measurement technique is based on the concept that in a MOSFET the Si surface field and thus GIDL current vary with oxide trapped charge. By monitoring the temporal evolution of GIDL current, the oxide charge trapping/detrapping characteristics can be obtained. An analytical model accounting for the time-dependence of an oxide charge detrapping induced GIDL current transient was derived. A specially designed measurement consisting of oxide trap creation, oxide trap filling with electrons or holes and oxide charge detrapping was performed. Two hot carrier stress methods, channel hot electron injection and band-to-band tunneling induced hot hole injection, were employed in this work. Both electron detrapping and hole detrapping induced GIDL current transients mere observed in the same device. The time-dependence of the transients indicates that oxide charge detrapping is mainly achieved via field enhanced tunneling. In addition, we used this technique to characterize oxide trap growth in the two hot carrier stress conditions. The result reveals that the hot hole stress is about 10⁴ times more efficient in trap generation than the hot electron stress in terms of injected charge     

A new approach to threshold voltage modelling of short-channel MOSFETS

A simple analytical model has been developed to predict the threshold voltage on drain bias dependence of an arbitrarily doped short-channel MOSFET. Based on an analytical solution of the two-dimensional Poisson equation, the potential distribution in the channel depletion region has been derived. The maximum surface field and the minimum surface potential are used to determine the threshold voltage. The influence of drain voltage on threshold voltage has been included by an equivalent shrinkage of the virtual channel length hereafter called “voltage-length transformation”. This simple but general procedure enables us to account for the drain effect and to extend other threshold voltage models derived under assumption of low drain-source voltage. Predictions for threshold voltage have been compared with results of two-dimensional numerical analysis and experimental data. The comparison has been made for a wide variety of doping profiles, channel length, substrate and drain bias, gate oxide thickness and junction depth. Excellent agreement has been obtained down to submicron channel length.     

Charge trapping in organic transistor memories: On the role of electrons and holes

In this work, we study charge trapping in organic transistor memories with a polymeric insulator as gate dielectric. We found that the mechanism of charge trapping is tunneling from the semiconductor channel into the gate dielectric. Depending on the semiconductor and its processing, charge trapping can result in large bi-directional threshold voltage shifts, in case the semiconductor is ambipolar, or in shifts in only one direction (unipolar semiconductor). These results indicate that optimal memory performance requires charge carriers of both polarities, because the most efficient method to lower the programming field is by overwriting a trapped charge by an injected charge of opposite polarity.