Thermomechanical reliability of underfilled BGA packages

The effect of underfill on various thermomechanical reliability issues in super ball grid array (SBGA) packages is studied in this paper. Nonlinear finite element models with underfill and no underfill are developed taking into consideration the process-induced residual stresses. In this study, the solder is modeled as time and temperature-dependent, while other materials are modeled temperature and direction-dependent, as appropriate. The stress/strain variations in the package due to thermal cycling are analyzed. The effect of underfill is studied with respect to magnitude and location of time-independent plastic strain, time-dependent creep strain and total inelastic strain in solder balls. The effect of copper core on the solder ball strains is presented. The possibility of delamination at the interposer-underfill interface as well as substrate-underfill interface is studied with the help of qualitative interfacial stress analysis. Results on SBGA packages indicate that the underfill does not always enhance BGA reliability, and that the properties of the underfill have a significant role in the overall reliability of the BGA packages. The predicted number of thermal cycles to solder joint fatigue are compared with the existing experimental data on similar nonunderfilled BGA packages.     

Effects of Phase Change of Pb-Free Flip-Chip Solders During Board-Level Interconnect Reflow

The impact of phase change (from solid to liquid) on the reliability of Pb-free flip-chip solders during board-level interconnect reflow is investigated. Most of the current candidates for Pb-free solder are tin-based with similar melting temperatures near 230 degC. Thus, Pb-free flip-chip solders melt again during the subsequent board-level interconnect reflow cycle. Solder volume expands more than 4% during the phase change from solid to liquid. The volumetric expansion of solder in a volume constrained by chip, substrate, and underfill creates serious reliability issues. The issues include underfill fracture and delamination from chip or substrate. Besides decreasing flip-chip interconnect reliability in fatigue, bridging through underfill cracks or delamination between neighboring flip-chip interconnects by the interjected solder leads to failures. In this paper, the volume expansion ratio of tin is experimentally measured, and a Pb-free flip-chip chip-scale package (FC-CSP) is used to observe delamination and solder bridging after solder reflow. It is demonstrated that the presence of molten solder and the interfacial failure of underfill can occur during solder reflow. Accordingly, Pb-free flip-chip packages have an additional reliability issue that has not been a concern for Pb solder packages. To quantify the effect of phase change, a flip-chip chip-scale plastic ball grid array package is modeled for nonlinear finite-element analysis. A unit-cell model is used to quantify the elongation strain of underfill and stresses at the interfaces between underfill and chip or underfill and substrate generated by volume expansion of solder. In addition, the strain energy release rate of interfacial crack between chip and underfill is also calculated     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

底部填充物对CSP-LED芯片抗跌落性能研究

为了提高芯片级封装发光二极管(CSP-LED)焊点疲劳寿命,利用有限元仿真软件ABAQUS模拟计算了CSP-LED芯片在跌落冲击载荷下焊点的塑性应变,并研究了裂纹拓展趋势。以焊点失效前跌落次数为指标,利用Coffin-Manson经验公式计算焊点寿命,研究了底部填充物对CSP-LED芯片在不同冲击载荷下焊点寿命的影响。结果表明,随着冲击载荷增大,焊点疲劳寿命减少,使用填充物能使芯片焊点寿命提高4~6倍,其影响通过跌落实验和仿真结果的对比得到了验证。     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

Effect of substrate flexibility on solder joint reliability

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue lifetime significantly. The reliability of solder joint in flip chip assembly for both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Experimental results strongly showed that the thermal fatigue lifetime of solder joints in flip chip on flex assembly was much improved over that in flip chip on rigid substrate assembly. Debonding area of solder joints in flip chip on rigid board and flip chip on flex assemblies were investigated, and it was found that flex substrate could slow down solder joint crack propagation rate. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique. TMA results showed that flex substrate buckles or bends during temperature cycling and this phenomenon was discussed from the point of view of mechanics of the flip chip assembly during temperature cycling process. It was indicated that the thermal strain and stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

Effects of underfill material properties on the reliability ofsolder bumped flip chip on board with imperfect underfill encapsulants

Three different types of underfill imperfections were considered; i.e., (1) interfacial delamination between the underfill encapsulant and the solder mask on the PCB (crack initiated at the tip of underfill fillet), (2) interfacial delamination between the chip and the underfill encapsulant (crack initiated at the chip corner), and (3) the same as (2) but without the underfill fillet. Five different combinations of coefficient of thermal expansion (CTE) and Young's modulus with the aforementioned delaminations were investigated. A fracture mechanics approach was employed for computational analysis. The strain energy release rate at the crack tip and the maximum accumulated equivalent plastic strain in the solder bumps of all cases were evaluated as indices of reliability. Besides, mechanical shear tests were performed to characterize the shear strength at the underfill-solder mask interface and the underfill-chip passivation interface. The main objective of the present study is to achieve a better understanding in the thermo-mechanical behavior of flip chip on board (FCOB) assemblies with imperfect underfill encapsulants     

Adhesion characterization of no-flow underfills used in flip chipassemblies and correlation with reliability

Adhesion is one of the key properties of underfills used in flip chip assemblies. This paper characterizes the adhesion strengths of no-flow underfill materials to various die passivations using the shear test techniques. A novel shear test vehicle with planner underfill layers between the die and substrate is presented. The adhesion strengths and failure modes of the no-flow underfill materials during shear testing correlate well with their thermal shock reliability test results. Underfill adhesion related failures such as delamination and crack are investigated and correlated between flip chip assemblies and shear test vehicle assemblies without solder joint interconnects     

倒扣芯片连接底充胶分层和焊点失效

在热循环疲劳加载条件下 ,使用 C- SAM高频超声显微镜测得了 B型和 D型两种倒扣芯片连接在焊点有无断裂时芯片 /底充胶界面的分层和扩展 ,得到分层裂缝扩展速率 .同时在有限元模拟中使用断裂力学方法计算得到不同情况下的裂缝顶端附近的能量释放率 .最后由实验裂缝扩展速率和有限元模拟给出的能量释放率得到可作为倒扣芯片连接可靠性设计依据的 Paris半经验方程     

Effect of substrate flexibility on solder joint reliability. Part II: finite element modeling

Solder joint fatigue failure is a serious reliability concern in area array technologies, such as flip chip and ball grid array packages of integrated-circuit chips. The selection of different substrate materials could affect solder joint thermal fatigue life significantly. The mechanism of substrate flexibility on improving solder joint thermal fatigue was investigated by thermal mechanical analysis (TMA) technique and finite element modeling. The reliability of solder joints in real flip chip assembly with both rigid and compliant substrates was evaluated by accelerated temperature cycling test. Finite element simulations were conducted to study the reliability of solder joints in flip chip on flex assembly (FCOF) and flip chip on rigid board assembly (FCOB) applying Anand model. Based on the finite element analysis results, the fatigue lives of solder joints were obtained by Darveaux’s crack initiation and growth model. The thermal strain/stress in solder joints of flip chip assemblies with different substrates were compared. The results of finite element analysis showed a good agreement with the experimental results. It was found that the thermal fatigue lifetime of FCOF solder joints was much longer than that of FCOB solder joints. The thermal strain/stress in solder joints could be reduced by flex buckling or bending and flex substrates could dissipate energy that otherwise would be absorbed by solder joints. It was concluded that substrate flexibility has a great effect on solder joint reliability and the reliability improvement was attributed to flex buckling or bending during temperature cycling.     

Dependence of Flip Chip Solder Reliability on Filler Settling

Thermomechanical reliability of solder joints in flip-chip packages is usually analyzed by assuming a homogeneous underfill ignoring the settling of filler particles. However, filler settling does impact flip chip reliability. This paper reports a numerical study of the influence of filler settling on the fatigue estimation of flip-chip solder joints. In total, nine underfill materials ( 35 vol% silica filler in three epoxies with three filler settling profiles for each epoxy) are individually introduced in a 2-D finite element (FE) model to compare the thermal response of flip chip solder joints that are surrounded by the underfill. The results show that the fatigue indicators for the solder joints (inelastic shear strain increments and inelastic shear strain energy density) corresponding to a gradual, nonuniform filler profile studied in this paper can be smaller than those associated with the uniform filler profile, suggesting that certain gradual filler settling profiles in conjunction with certain resin grades may favor a longer solder fatigue lifetime. The origin of this intriguing observation is in the fact that the solder fatigue indicators are a function of the thermal mismatch among the die, substrate, solder, and underfill materials. The thermal mechanics interplayed among these materials along with a gradual filler profile may allow for minimizing thermal mismatch; and thus lead to lower fatigue indicators.      

Numerical Investigation of Underfill Failure Due to Phase Change of Pb-Free Flip Chip Solders During Board-Level Reflow

In this paper, the effects of phase change of Pb-free flip chip solders during board-level interconnect reflow are investigated using numerical technique. Most of the current Pb-free solder candidates are based on Sn and their melting temperatures are in the range of 220 $^{circ}$ C–240 $^{circ}$ C. Thus, Pb-free flip chip solders melt again during subsequent board-level interconnect (BGA) reflow cycle. Since solder volume expands as much as 4% during the phase change from solid to liquid, the volumetric expansion of solder in a predefined volume by chip, substrate, and underfill creates serious reliability issues. One issue is the shorting between neighboring flip chip interconnects by the interjected solder through underfill crack or delaminated interfaces. The authors have observed the interjection of molten solder and the interfacial failure of underfill during solder reflow process. In this paper, a flip chip package is modeled to quantify the effect of the volumetric expansion of Pb-free solder. Three possible cases are investigated. One is without existence of micro crack and the other two are with the interfacial crack between chip and underfill and the crack through the underfill. The strain energy release rate around the crack tip calculated by the modified crack closure integral method is compared with interfacial fracture toughness. Parametric studies are carried out by changing material properties of underfill and interconnect pitch. Also, the effects of solder interconnect geometry and crack length are explored. For the case with interfacial crack, the configuration of a large bulge with small pitch is preferred for the board-level interconnect, whereas a large pitch is preferred for cracks in the mid plane of the underfill.      

FCOB器件在热循环载荷下的界面层裂研究

界面层裂是塑封半导体器件的主要失效模式之一。采用通用有限元软件MSC.MARC,研究了FCOB(基板倒装焊)器件在热循环(–55~+125℃)载荷作用下,底充胶与芯片界面的层裂问题。结果表明:底充胶与芯片界面最易出现分层,分层扩展的位置都在该界面的边缘拐角处;如果分层导致底充胶开裂,开裂的方向大约是35°。     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

Effects of solder joint shape and height on thermal fatigue lifetime

Solder joint thermal fatigue failure is a major concern for area array technologies such as flip chip and ball grid array technologies. Solder joint geometry is an important factor influencing thermal fatigue lifetime. In this paper, the effects of solder joint shape and height on thermal fatigue lifetime are studied. Solder joint fatigue lifetime was evaluated using accelerated temperate cycling and adhesion test. Scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), scanning acoustic microscopy (nondestructive evaluation) and optical microscopy were utilized to examine the integrity of the joint and to detect cracks and other defects before and during accelerated fatigue tests. Our accelerated temperature cycling test clearly shows that solder joint fatigue failure process consists of three phases: crack initiation, crack propagation and catastrophic failure. Experimental results indicated that both hourglass shape and great standoff height could improve solder joint fatigue lifetime, with standoff height being the more effective factor. Experimental data suggested that shape is the dominant factor affecting crack initiation time while standoff height is the major factor influencing crack propagation time.     

Reliability analysis and design for the fine-pitch flip chip BGA packaging

The geometry of solder joints in the flip chip technologies is primarily determined by the associated solder volume and die/substrate-side pad size. In this study, the effect of these parameters on the solder joint reliability of a fine-pitched flip chip ball grid array (FCBGA) package is extensively investigated through finite element (FE) modeling and experimental testing. To facilitate thermal cycling (TC) testing, a simplified FCBGA test vehicle with a very high pin counts (i.e., 2499 FC solder joints) is designed and fabricated. By the vehicle, three different structural designs of flip chip solder joints, each of which consists of a different combination of these design parameters, are involved in the investigation. Furthermore, the associated FE models are constructed based on the predicted geometry of solder joints using a force-balanced analytical approach. By way of the predicted solder joint geometry, a simple design rule is created for readily and qualitatively assessing the reliability performance of solder joints during the initial design stage. The validity of the FE modeling is extensively demonstrated through typical accelerated thermal cycling (ATC) testing. To facilitate the testing, a daisy chain circuit is designed, and fabricated in the package for electrical resistance measurement. Finally, based on the validated FE modeling, parametric design of solder joint reliability is performed associated with a variety of die-side pad sizes. The results show that both the die/substrate-side pad size and underfill do play a significant role in solder joint reliability. The derived results demonstrate the applicability and validity of the proposed simple design rule. It is more surprising to find that the effect of the contact angle in flip chip solder joint reliability is less significant as compared to that of the standoff height when the underfill is included in the package.     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。