基于DSP和USB接口的视觉检测系统的设计

实时视觉检测系统的一个主要瓶颈是图像的处理速度。该文将DSP技术应用于计算机视觉领域，闸述了利用DSP和现场可编程门阵列(FPGA）实现的基于USB接口的嵌入式视觉检测系统。详细介绍了系统的构成以及该系统的主要工作流程。     

基于FPGA图像处理技术在钢板表面缺陷检测系统中的应用

为了解决钢板表面缺陷视觉检测系统中图像处理的瓶颈问题,采用基于FPGA的嵌入式处理系统完成大数据量、实时、在线的处理任务,从而满足高速、宽幅、高分辨率的检测要求.嵌入式系统以Altera公司最新的Stratix FPGA作为核心处理器,在分析FPGA专有的硬件结构基础上,对图像处理中的模板卷积算法进行了优化设计,采用Verilog语言对算法完成建模与实现,并在Quartus Ⅱ平台进行了仿真验证.实验与算法仿真证明嵌入式处理系统的可行性与工程实用性,从而表面缺陷检测系统中的图像信息实时处理这一关键问题得以解决.     

产业信息

正Altera加入嵌入式视觉联盟Altera公司宣布,加入嵌入式视觉联盟(Embedded Vision Alliance,EVA)——该行业组织是计算机视觉实际应用开发的技术供应商联盟。Altera为这一组织带来了专业的可编程逻辑技术,支持系统设计人员使用FPGA、SoC、IP,以及设计工具实现工业、监控、汽车、广播和消费类等领域的嵌入式视觉应用。Altera FPGA在嵌入式视觉处理流水线方面非常灵活,性能也非常高,这主要包括图像传感器接口、图像信号处理、压缩、传输,以及视频内容分析等。FPGA并行体系结构有助于视觉处理器算法的加速实现,采用面向     

嵌入式CCD图像数据采集系统设计

为了满足嵌入式机器视觉后续图像处理的需要,结合高速DSP和FPGA的特点,设计了一套面向嵌入式机器视觉系统的图像数据采集系统.充分利用FPGA内部异步FIFO资源作为数据缓冲区,将异步FIFO数据以TMS320DM642的PDT方式写入数据SDRAM.当SDRAM接收一帧图像可以直接用DSP进行图像处理.DSP读写SDRAM速度高达150 MHz,PDT传输方式不占用DSP CPU时间,不影响图像处理速度.该系统具有电路结构简单、数据传输实时性好和易于升级等优点.     

基于FPGA嵌入式系统的研究与应用

针对FPGA自身用户可编程的特性,分析了FPGA嵌入式系统的优势和应用领域,研究了利用FPGA实现嵌入式系统的基本原理和设计方法,重点探讨了其结构的转换难点.通过具体应用,分析了乘法累加驱动滤波器的实现原理和处理过程,设计了FPGA嵌入式系统的具体实现方式.     

基于DSP/FPGA的嵌入式实时目标跟踪系统

提出了一套基于DSP／FPGA的协处理器结构用以实现实时目标跟踪的嵌入式视觉系统。系统由DSP作为主处理器进行全局控制，利用具有流水线并行处理结构的FPGA作为协处理器实时完成DSP分配的处理任务。系统由FPGA快速完成最初的运动估计的结果，DSP在此基础上进一步分析和校正，并将校正信息反馈给FPGA，实现快速而准确的跟踪。     

FPGA的边界扫描配置算法及嵌入式实现

针对基于FPGA开展的计算机硬件实验,本文提出了远程计算机硬件实验系统,系统由实验客户端、嵌入式实验服务器和FPGA实验板三部分组成,为了解决系统中目标FPGA的远程配置这一关键问题,本文着力研究FPGA的边界扫描配置模式以及它的实现算法,编写运行在嵌入式实验服务器端的C语言程序,成功实现了对目标FPGA的配置.     

嵌入式机器视觉测控系统设计研究

嵌入式系统的逐步广泛应用,为智能机器人视觉控制系统的研究提供了一条新的思路。该文将嵌入式系统与机器视觉控制结合起来,设计探讨了基于嵌入式系统的机器视觉测控系统,给出了总体的软件和硬件设计方案,并在此基础上,重点对系统设计中的关键技术问题进行了研究分析,从图像采集模块和实时跟踪算法控制模块两个角度进行了设计,对于进一步提高嵌入式系统与智能机器人控制系统的研究和应用具有一定借鉴意义。     

一种基于FPGA和软核CPU的嵌入式系统设计方法

本文对一种基于FPGA和软核CPU的嵌入式系统设计的方法进行了描述,整个系统以FPGA和NIOS为中心进行设计,外围接口包括JTAG、串口、USB口等.系统选用ALTERA公司的Cyclone系列的芯片作为核心处理芯片,配合ALTERA公司推出的NIOS软核嵌入式处理器构成整个系统的核心.操作系统采用μC/OS嵌入式系统,并移植到FPGA平台上.     

基于嵌入式ARM和FPGA数控系统设计研究

本文完成了一种嵌入式数控系统的设计,该系统结合运用ARM和FPGA,系统的控制软件功能主要通过使用ARM模块实现,通过对FPGA的逻辑运算能力进行充分利用,实现了对数控系统中的脉冲信号的有效生成及分配过程,并设置了能够为为系统提供额定工作电压的电源模块,使控制机械设备动作的精确度得以有效提升,同时显著提高了嵌入式系统的...     

Enhancing Security of FPGA-Based Embedded Systems with Combinational Logic Binding

With the increasing use of field-programmable gate arrays (FPGAs) in embedded systems and many embedded applications, the failure to protect FPGA-based embedded systems from cloning attacks has brought serious losses to system developers. This paper proposes a novel combinational logic binding technique to specially protect FPGA-based embedded systems from cloning attacks and provides a pay-per-device licensing model for the FPGA market. Security analysis shows that the proposed binding scheme is robust against various types of malicious attacks. Experimental evaluations demonstrate the low overhead of the proposed technique.     

Implementation of secure applications in self-reconfigurable systems

In a highly connected World, network security is a must even for embedded systems. However, cryptographic algorithms are computationally intensive and the processors used in FPGA-based embedded systems are known to have a modest performance. In fact, this paper presents a study showing that unless HW acceleration is used, the throughput of secure applications on FPGA-based embedded systems is poor when compared to the current networking standards. But the multi-algorithm nature of most applications poses many difficulties to classic HW acceleration, particularly large area utilization and difficulty in supporting new algorithms. Fortunately, these problems can be easily solved using partial run-time reconfiguration. This paper proposes an architecture based on self-reconfiguration that allows the implementation of hardware accelerated secure applications in FPGA-based embedded systems. Cryptographic coprocessors are efficiently deployed without incurring in the problems mentioned above, and moreover, without needing any external components. To prove the feasibility of this proposal, a proof-of-concept implementation of the well-known SSH application has been developed in a low-cost commercial device running a standard operating system.     

基于FPGA的透视投影变换算法的设计与实现

在阐述了嵌入式地形三维显示系统的透视投影变换算法的基础上,着重论述了基于FP-GA设计实现透视投影变换算法的方法,并在XILINX公司的SPARTANXC3S500E上实现了本算法的基本功能。实验数据表明该硬件算法系统具有实时性高和时间开销低等优点。     

Enhancing image processing architecture using deep learning for embedded vision systems

In recent years, the success and capabilities of embedded vision have showed up in embedded applications. The embedding of vision into electronic devices such as embedded medical applications is being driven by the availability of high-performance processors, integrating with deep learning algorithms, as well as advances in image processing technology. But, including image processing in embedded vision systems need huge amount of computational capabilities even to process a single image to detect an object and it's extremely challenging to implement in embedded systems. Implementing deep learning algorithms and testing it on a task specific data set could provide enhanced results. In this paper, an approach for enhancing image processing architecture using deep learning for embedded vision systems is proposed and analyzed. Implementing deep learning algorithms and testing it on embedded vision yielded effective results.     

FPGA-based module for SURF extraction

We present a complete hardware and software solution of an FPGA-based computer vision embedded module capable of carrying out SURF image features extraction algorithm. Aside from image analysis, the module embeds a Linux distribution that allows to run programs specifically tailored for particular applications. The module is based on a Virtex-5 FXT FPGA which features powerful configurable logic and an embedded PowerPC processor. We describe the module hardware as well as the custom FPGA image processing cores that implement the algorithm’s most computationally expensive process, the interest point detection. The module’s overall performance is evaluated and compared to CPU and GPU-based solutions. Results show that the embedded module achieves comparable distinctiveness to the SURF software implementation running in a standard CPU while being faster and consuming significantly less power and space. Thus, it allows to use the SURF algorithm in applications with power and spatial constraints, such as autonomous navigation of small mobile robots.     

Fuzzy logic-based embedded system for video de-interlacing

Video de-interlacing algorithms perform a crucial task in video processing. Despite these algorithms are developed using software implementations, their implementations in hardware are required to achieve real-time operation. This paper describes the development of an embedded system for video de-interlacing. The algorithm for video de-interlacing uses three fuzzy logic-based systems to tackle three relevant features in video sequences: motion, edges, and picture repetition. The proposed strategy implements the algorithm as a hardware IP core on a FPGA-based embedded system. The paper details the proposed architecture and the design methodology to develop it. The resulting embedded system is verified on a FPGA development board and it is able to de-interlace in real-time.     

基于Linux 的嵌入式视觉系统

结合当前嵌入式产品的发展方向,提出了一种基于ARM9和Linux的嵌入式视觉系统,阐述了其硬件架构与软件组成,通过配置和加载各种设备驱动程序,利用V4L接口函数实现图像采集与显示。设计的嵌入式视觉系统体积小,成本低,可移植性强,通过实验波形和数据验证了其具有良好的图像采集和显示性能。     

Real-time human action recognition on an embedded, reconfigurable video processing architecture

In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. Here we propose a real-time, embedded vision solution for human action recognition, implemented on an FPGA-based ubiquitous device. There are three main contributions in this paper. Firstly, we have developed a fast human action recognition system with simple motion features and a linear support vector machine classifier. The method has been tested on a large, public human action dataset and achieved competitive performance for the temporal template class of approaches, which include “Motion History Image” based techniques. Secondly, we have developed a reconfigurable, FPGA based video processing architecture. One advantage of this architecture is that the system processing performance can be reconfigured for a particular application, with the addition of new or replicated processing cores. Finally, we have successfully implemented a human action recognition system on this reconfigurable architecture. With a small number of human actions (hand gestures), this stand-alone system is operating reliably at 12 frames/s, with an 80% average recognition rate using limited training data. This type of system has applications in security systems, man–machine communications and intelligent environments.

基于ARM的嵌入式图像采集系统设计

设计针对广泛应用于安全防控系统、视频监控系统、视频网络系统以及机器视觉等领域中的核心图像采集处理单元提出的。目标是设计出一个基于32位嵌入式微处理器ARM（S3C2410）和嵌入式操作系统ARM—Linux的视频图像采集系统。旨在用最少的硬件,完成高质量的图像采集功能。介绍了视频图像采集处理系统的总体设计及其具体实现。     

基于MPSoC并行调度的矩阵乘法加速算法研究

矩阵乘法是数值分析以及图形图像处理算法的基础,通用的矩阵乘法加速器设计一直是嵌入式系统设计的研究热点。但矩阵乘法由于计算复杂度高,处理效率低,常常成为嵌入式系统运算速度的瓶颈。为了在嵌入式领域更好地使用矩阵乘法,提出了基于MPSoC(MultiProcessor System-on-Chip)的软硬件协同加速的架构。在MPSoC的架构下,一方面,设计了面向硬件约束的矩阵分块方法,从而实现了通用的矩阵乘法加速器系统;另一方面,通过利用MPSoC下的多核架构,提出了相应的任务划分和负载平衡调度算法,提高了并行效率和整体系统加速比。实验结果表明,所提架构及算法实现了通用的矩阵乘法计算,并且通过软硬件协同设计实现的多核并行调度算法与传统单核设计相比在计算效率方面得到了显著的提高。